30.3.18.21 Flash ECC Fault Syndrome Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | FFLTSYN |
| Offset: | 0x0058 |
| Reset: | 0x00000000 |
| Property: | PAC Write Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PERR3 | PERR2 | PERR1 | PERR0 | CTLSTAT[2:0] | |||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CERR | DERR | SERR | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DEDSYN | SECSYN[8] | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SECSYN[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 28, 29, 30, 31 – PERR Per Word Parity Error Status
Note: Word size is defined by the Write Word size of the flash (64-bits).
| Value | Description |
|---|---|
| 0 | No Parity Error Word n |
| 1 | Parity Error on Word n |
Bits 26:24 – CTLSTAT[2:0] Parity vs ECC Control Status
Note: Panel is always programmed with 000 for ECC and 111 for parity.
000,001,010,100 = Calculation used ECC (i.e. programming used quad write)
011,101,110,111 = Calculation used Parity (i.e. programming used single write)
Bit 18 – CERR ECC Control bit Error
| Value | Description |
|---|---|
| 0 | No Control bit Error (ECCSTAT either 111 or 000) |
| 1 | Single Control Bit Error |
Bit 17 – DERR Double Error Detected
For Reads only when ECCSTAT = ECC
| Value | Description |
|---|---|
| 0 | No Error |
| 1 | Double Error Detected |
Bit 16 – SERR Single Error Corrected
For Reads only when ECCSTAT = ECC
| Value | Description |
|---|---|
| 0 | No Error |
| 1 | Double Error Detected |
Bit 15 – DEDSYN DED Syndrome
This is Overall Parity Calculated from Data and all Parity bits read from Flash.
| Value | Description |
|---|---|
| 0 | Calculated Overall Parity Concurs with Read Overall Parity |
| 1 | Calculated Overall Parity Differs from Read Overall Parity |
Bits 8:0 – SECSYN[8:0] Single Error Correction Syndrome
For Reads only when CTLSTAT = ECC or System bits ECCCTL[1:0]=ECC
This value is the bitwise XOR of SECIN and SECOUT.
If DEDSYN=1:
000000000 = No Data Error, but DED bit in Error
Non-Zero = SECSYN points to the bit position in the calculation vector that was corrected
If DEDSYN = 0:
000000000 = No Data Error or DED bit Error
Non-Zero = Double Error Detected.
Note: The number of active bits is dependent on the data width of the Flash
panel.