30.3.18.20 Flash Fault Capture Parity Register

Table 30-44. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Bit 31 – DEDOUT Calculated Overall Parity used in Double Error Detection

For Writes this value is based on write data and the calculated SEC Parity bits.

For Reads this value is based on read data and the calculated SEC Parity bits.

Note:

See the Flash ECC Vector table for calculation vector bit order vs data bit order vs control bit order.
“DED”, “Overall Parity”, and “Parity[0]” are used interchangeably.

For Writes this value is based on write data.

For Reads this value is based on read data.

Note:

See the Flash ECC Vector table for calculation vector bit order vs data bit order vs control bit order.
The number of active bits is dependent on the data width of the Flash panel.
The terms “SEC*[8:0]” and “Parity[9:1]” are used interchangeably.

For Writes this value is always 0.

For Reads this value is the overall parity read from flash.

Note:

See the Flash ECC Vector table for calculation vector bit order vs data bit order vs control bit order.
“DED”, “Overall Parity”, and “Parity[0]” are used interchangeably.

For Writes this value is always0.

For Reads this value is the Single Error Parity bits read from Flash.

Note:

See the Flash ECC Vector table for calculation vector bit order vs data bit order vs control bit order.
The number of active bits is dependent on the data width of the Flash panel.
The terms “SEC*[8:0]” and “Parity[9:1]” are used interchangeably.