30.3.18.1 Control A Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x0000 |
| Reset: | 0x00008000 |
| Property: | PAC Write Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RDBUFWS[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| AUTOWS | ADRWS | FWS[3:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ARB | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bits 19:16 – RDBUFWS[3:0] Data Returned from the Read Buffer match the Flash Wait States
When returning data from the AHB n read buffer, insert wait states to match ADRWS and FWS from Flash based on RDBUFWS[n].
| Value | Description |
|---|---|
| 0 | Zero wait states for hits to AHBn read buffer. |
| 1 | ADRWS + FWS wait state for hits to AHBn read buffer, n = 0 to 2. |
Bit 15 – AUTOWS Automatic Wait State Enable
Taws = Tacc + 5ns + 2 clocks
| Value | Description |
|---|---|
| 0 | Use FWS: Total flash wait states are ADRWS + FWS |
| 1 | Use Automatic wait states: Total flash wait states are ADRWS + Taws |
Bit 14 – ADRWS Address Wait State Enable
For Total flash wait states see AUTOWS.
| Value | Description |
|---|---|
| 0 | Add 0 Address Wait States - allowing for higher performance at lower clock frequencies |
| 1 | Add 1 Address Wait State - allowing for higher clock frequencies |
Bits 11:8 – FWS[3:0] Flash Access Time Defined in terms of AHB Clock Wait States
1111= Fifteen Wait States
1110= Fourteen Wait States
...
0001= One Wait State
0000= Zero Wait States
Note: This is not the wait states seen by the CPU. For Total Flash wait states see
AUTOWS.
Bit 2 – ARB AHB Arbitration Scheme
| Value | Description |
|---|---|
| 0 | Round Robin Arbitration. |
| 1 | Fixed priority AHB0 highest to AHB2 lowest |