25.10.10 Channel Destination Cell Stride Size Register
CHCTRLAk.ENABLE=1 write protected.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CHDSTRDk |
| Offset: | 0x74 + k*0x50 [k=0..15] |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DSTRD[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DSTRD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – DSTRD[15:0] Destination Cell Stride Size
This value provide in this register is added to the last address of the cell transfer to determine the address of the next cell to read.
Next Cell Start Address = Current Cell Start Address + CHXSIZk.CSZ +
DSTRD 0xFFFF =65,535 byte destination cell stride size
0x0000 = destination cell stride defaults to the
same value as CHXSIZk.CSZ.
If CHCTRLBk.WAS[2:0] = 001 or 100, the stride size must be halfword aligned where DSTRD[0] = 0.
If CHCTRLBk.WAS[2:0] = 101, the stride size must be word aligned where DSTRD[1:0] = 00.
If CHCTRLBk.WAS[2:0] = 010 and only word transfers are desired, the stride size must be word aligned where DSTRD[1:0] = 00.