25.10.14 Channel CRC/Checksum Data Register

CHCTRLAk.ENABLE=1 write protected.

Table 25-28. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CHCRCDATk
Offset:	0x84 + k*0x50 [k=0..15]
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24
	CRCDAT[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	CRCDAT[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	CRCDAT[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CRCDAT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – CRCDAT[31:0] CRC Data

Writing to this register will seed the CRC/Checksum generator.

Reading from this register will return the current value of the CRC/checksum.

If CHCTRLCRC.CRCMD is set to the IP header checksum mode, only the lower 16-bits contain information; the upper 16-bits are always read back zero. Data written to this register is converted and read back in one’s complement form. (i.e. current checksum value).

If CHCTRLCRC.CRCMD is set to a 16-bit CRC mode, the lower 16-bits contain CRC value; the upper 16-bits are always zero. If CHCTRLCRC.CRCXOR is set, read back provides the 1’s complement of the CRC value. If CHCTRLCRC.CRCROUT is set, the lower 16-bits are read back in reverse order.

If CHCTRLCRC.CRCMD is set to a 32-bit CRC mode, the register contains the 32-bit CRC value. If CHCTRLCRC.CRCXOR is set, read back provides the 1’s complement of the CRC value. If CHCTRLCRC.CRCROUT is set, the 32-bit value is read back in reverse bit order.