25.10.19 Channel Status Cell Count Register
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | CHSTATk |
Offset: | 0x98 + k*0x50 [k=0..15] |
Reset: | 0x00000000 |
Property: | PAC Write-Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DREAD | CELLBUSY | BLKBUSY | |||||||
Access | R | R | R | ||||||
Reset | 0 | 0 | 0 |
Bit 2 – DREAD Descriptor Read Status Bit
Value | Description |
---|---|
0 | Descriptor has not been read or is not available to read. |
1 | Descriptor read and loaded into channel registers. |
Bit 1 – CELLBUSY Channel Cell Transfer Busy Status Bit
Value | Description |
---|---|
0 | Channel is idle |
1 | Channel is performing a cell transfer |
Bit 0 – BLKBUSY Channel Block Transfer Busy Status Bit
Value | Description |
---|---|
0 | Channel is idle. |
1 | Channel is performing a block transfer. Setting CHCTRLAk.ENABLE=0 will suspend the block transfer. On a channel reset, this bit will clear at the completion of the reset sequence. Software can poll this bit to determine when the channel has finished resetting. |