16.13.8 Status A
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | STATUSA |
| Offset: | 0x0100 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| BREXT1 | BREXT0 | ||||||||
| Access | R/K | R/K | |||||||
| Reset | 0 | x |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CRSTEXT1 | CRSTEXT0 | ||||||||
| Access | R/K | R/K | |||||||
| Reset | 0 | x |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PERR | BERR | FAIL | DONE | ||||||
| Access | R/K | R/K | R/K | R/K | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 16, 17 – BREXTx Boot ROMx Phase Extension for CPUx, x =0,1
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Boot ROM Phase Extension bit.
Writing a '1' to this bit clears the Boot ROM Phase Extension bit. This bit is set when a debug adapter Cold-Plugging is detected, which extends the Boot ROM phase. Refer to the Chapter “Boot ROM” for more details. When CPUx is not present it always reads as ‘1’ else if STATUSB.APDIS is high then it always reads as ‘0’.
Bits 8, 9 – CRSTEXTx CPUx Reset Phase Extension, x = 0,1
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the CPUx Reset Phase Extension bit.
This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPUx reset phase.
When CPUx is not present it always reads as ‘1’ else if STATUSB.APDIS is high then it always reads as ‘0’.
Bit 3 – PERR Protection Error
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Protection Error bit.
This bit is set when any illegal access is detected (from a debug adapter or any host) such as an access to an unimplemented register.
This bit is set when writing an invalid command into CTRL.CMD.
Bit 2 – BERR Bus Error
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Bus Error bit.
This bit is set when a bus error is detected.
Bit 1 – FAIL Failure
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Failure bit.
This bit is set when a DSU operation failure is detected.
Bit 0 – DONE Done
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Done bit.