16.13.2 Address

Table 16-10. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	ADDR
Offset:	0x0004
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24
	ADDR[29:22]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	ADDR[21:14]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ADDR[13:6]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ADDR[5:0]						AMOD[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:2 – ADDR[29:0] Address

Initial word start address needed for memory operations or next word address to test during MBIST operation.

Bits 1:0 – AMOD[1:0] Access Mode

These bits are only available in MBIST mode operation mode, they are reserved otherwise.

0x0 = STATUSA.FAIL rises upon first error and algorithm stops (STATUSA.DONE rises). (EXIT_ON_ERROR)

0x1 = STATUSA.FAIL rises when an error is detected and algorithm stops until STATUSA.FAIL is cleared. Once cleared, the algorithm is resumed going to next test step. (PAUSE_ON_ERROR).

0x2-0x3 = Reserved