16.13.9 Status B

Table 16-17. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: STATUSB
Offset: 0x0104
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     APDISHPE DBGPRES 
Access RRR 
Reset x0x 
Bit 76543210 
     DCCD1DCCD0BCCD1BCCD0 
Access RRRR 
Reset 00xx 

Bit 11 – APDIS ARM Access Ports Disabled

Reading this bit provides the following information:

1: All Arm MEM-AP in the DAP are disabled. Access to the AHB-AP registers is still permitted but no AHB transfers are initiated. If a transfer is attempted from the DP then the DAP bus returns an error. Only the CPU can read this register.

0: Arm Access ports not disabled.

Bit 10 – HPE Hot-Plugging Enable

This bit is set when Hot-Plugging is enabled.

This bit is cleared when Hot-Plugging is disabled. This is the case when the TCK/SWCLK function is changed. Only a power-reset or an external reset can set it again.

Bit 8 – DBGPRES Debugger Present

When BRCTRL.APDIS = 1 this bit always reads 0, all access ports are consequently disabled.

This bit is set when a debugger probe is detected.

Only a POR or external reset can reset this bit.

Bits 2, 3 – DCCDx Debug Communication Channel x Dirty [x=1..0]

This bit is set when DCCx register is written.

This bit is cleared when DCCx register is read.

Reset by APB reset.

Bits 0, 1 – BCCDx BOOT Communication Channel x Dirty [x=1..0]

This bit is set when BCCx register is written.

This bit is cleared when BCCx register is read.

Reset by APB reset and modified by the Boot ROM at boot time.