43.7.18 ADC FIFO Control Register
The ADC FIFO is useful in applications that stream out ADC data at very high transfer rates to relive CPU bandwidth. Individual high data rate ADC result interrupts and CPU reads may slow bus access transfer requests.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PFFCTRL |
| Offset: | 0xE4 |
| Reset: | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PFFRDYDMA | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PFFCR | PFFEN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 16 – PFFRDYDMA DMA FIFO Data Ready Interrupt selection
Note:
- This bit is Enabled Protected: (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error).
| Value | Description |
|---|---|
| 0 | Selects CTLINTFLAG.PFFHFUL for the ADC DMA PFFRDY trigger signal to the DMAC |
| 1 | Selects CTLINTFLAG.PFFRDY for the ADC DMA PFFRDY trigger signal to the DMAC |
Bit 4 – PFFCR FIFO Enable for ADCn
When PFFEN = 1, setting this bit for the ADC enables the conversion output data of any channel k associated to the ADC to be stored into the optional data FIFO.
Note:
- This bit is Enabled Protected: (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error).
Bit 1 – PFFEN FIFO General Enable
When the FIFO is disabled no data is being saved into the FIFO and the its logic is being kept in reset state.
Note:
- This bit is Enabled Protected: (Writes are ignored when CTRLA.ENABLE = 1. Returns a bus error).
| Value | Description |
|---|---|
| 0 | FIFO is disabled |
| 1 | FIFO is enabled |