43.7.1 ADC Control Register A

Table 43-5. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	ONDEMAND	RUNSTDBY				ANAEN	ENABLE	SWRST
Access	R/W	R/W				R/W	R/W	R/W
Reset	1	0				0	0	0

Bit 7 – ONDEMAND On Demand Control (idle/standby mode)

The On Demand operation mode allows the ADC to be normally disabled, lowest power mode, until enabled by an EVSYS trigger event. The consequences of this however is that the analog logic is completely powered down when ONDEMAND=1 and clocks are suspended. Upon a EVSYS trigger event, it will require up to 20-50µs for the ADC to warm up meaning that the actual sample/convert sequence will not happen for:

ADC analog input signal sample point in time = (EVSYS Trigger event + CTRLD.WKUPEXP)

Which can be up to 50µs after the initial EVSYS trigger event. After the conversion is complete, if there are no pending EVSYS trigger events the ADC will again power down and the sequence will repeat as before.

When ONDEMAND = 1, the ADC works only on a rising edge EVSYS events. In addition, all other ADC trigger sources other than EVSYS triggers will not be acknowledged and therefore will render the ADC inactive. (See table below)

In Idle and Standby mode, if ONDEMAND = 1 and CTRLA.RUNSTDBY = 1, the ADC will be active and not powered down. If CTRLA.RUNSTDBY=0, the ADC is powered down and ADC clocks are suspended.

Note: CTRLD.WKUPEXP should be set by user to the equivalent of 50 µs or CTRLD.WKUPEXP[xxx] = 50 µs / TAD.

Table 43-6. ONDEMAND Matrix
SYSTEM STATUS	ONDEMAND	RUNSTDBY	ADCn Trigger Source	ADC BEHAVIOR
ACTIVE	1	x	ADCn Global Software Trigger.	Do Nothing
		x	ADCn Global Level Software Trigger	Do Nothing
		x	ADCn SCANTRG	Do Nothing except only when SCAN trigger source selected is EVSYS trigger, then RUN only when EVSYS trigger request is received.
		x	ADCn STRIG Synchronous Trigger	Do Nothing
		x	ADCn Trigger Event(s) from Event System (EVSYS)	RUN only when EVSYS trigger request is received.
	0	x	ADCn Global Software Trigger.	ADC active, Trigger sample/conv and wait for next trigger
		x	ADCn Global Level Software Trigger	ADC active, Trigger sample/conv continuously.
		x	ADCn SCANTRG	ADC active, Trigger sample/conv and wait for next trigger
		x	ADCn STRIG Synchronous Trigger	ADC active, Trigger sample/conv and wait for next trigger
		x	ADCn Trigger Event(s) from Event System (EVSYS)	ADC active, Trigger sample/conv and wait for next trigger.
IDLE, STANDBY	0	1	All triggers working	ADC active
	1	0	n/a	Do nothing
	1	1	ADCn Trigger Event(s) from Event System (EVSYS)	RUN only when EVSYS trigger request is received.

Value	Description
0	The ADC is always on, if ENABLE = 1. (Highly Recommended)
1	See table below.

Bit 6 – RUNSTDBY Run in Idle/Standby Mode

This bit controls how the ADC behaves during Standby Sleep mode.

This bit is not synchronized.

Value	Description
0	Discontinue module operation when device enters idle/standby mode (but do not stop the CTL_CLK to preserve the analog biasing). The ADC will complete the ongoing conversion before disabling the module.
1	The ADC is not stopped in Idle or Standby sleep mode. If CTRLA.ONDEMAND = 1, the ADC will be running when a peripheral is requesting it. If CTRLA.ONDEMAND = 0, the ADC will always be running in standby sleep mode.

Bit 2 – ANAEN Analog Cores Enable bit

Note: This bit must be set prior to setting any of the CTRLD.ANLENn bits.

Value	Description
0	The analog and bias circuitry for all ADC modules are powered down and clocks disabled. Trigger events will not be serviced.
1	Enables and powers up the individual ADC modules analog logic based on the settings of CTRLD.ANLENn = 1, (where n = 0,1,2,3). Whenever the ADC module"n" exits a power down state to a powered-up state, CTRLA.ANAEN = 1 and CTRLD.ANLENn = 1, then the system hardware will wait until CTRLD.WKUPEXP time has expired before starting an ADCn sample/conversion if a trigger event is pending. The ADCn required warm-up time is 20-50us before it will stabilize for a valid ADC sample/conversion sequence to start. CTRLA.ENABLE does not need to be set to power-up the analog logic and begin the CTRLD.WKUPEXP time out.

Value

Description

0

The analog and bias circuitry for all ADC modules are powered down and clocks disabled. Trigger events will not be serviced.

1

Enables and powers up the individual ADC modules analog logic based on the settings of CTRLD.ANLENn = 1, (where n = 0,1,2,3). Whenever the ADC module"n" exits a power down state to a powered-up state, CTRLA.ANAEN = 1 and CTRLD.ANLENn = 1, then the system hardware will wait until CTRLD.WKUPEXP time has expired before starting an ADCn sample/conversion if a trigger event is pending. The ADCn required warm-up time is 20-50us before it will stabilize for a valid ADC sample/conversion sequence to start. CTRLA.ENABLE does not need to be set to power-up the analog logic and begin the CTRLD.WKUPEXP time out.

Bit 1 – ENABLE A/D Module Operating Enable bit

Note:

The ENABLE bit should be set only after the ADC module has been configured. Changing the configuration bits after enabling the ADC could result in unpredictable behavior.
When ENABLE = 0 the internal control logic is reset, and all status generated by the module is cleared. All ADC Module clocks are disabled unless ANAEN = 1. In this case ANLENn = 0 disable clocks and ANLENn = 1 enables them. All ADC registers are available for reading and writing.

Value	Description
0	A/D converter is off.
1	A/D converter module is enabled.

Bit 0 – SWRST Software Reset

Writing a one to the SWRST bit resets the state of the ADC and all the registers to their initial state. The only exception is the DBGCTRL.DBGRUN bit, which will keep its value after a SWRST. The module will be disabled after the reset (ENABLE = 0). When writing a one to SWRST, no other bits in the same register will be written, as SWRST will clear all the bits in the same register.

After writing a one to SWRST, SWRST will read back one until the module and the registers are reset. Any register write access during the ongoing reset will be discarded and an error will be generated. Read access can be performed without an error generated and must return reset value. Writing a one to SWRST will have priority above all other actions and will always happen immediately.

Writing a zero to SWRST has no effect.

Note: During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST is cleared by hardware.

Value	Description
0	There is no reset operation ongoing.
1	The reset operation is ongoing.

Name:	CTRLA
Offset:	0x0
Reset:	0x00000000
Property:	PAC Write-Protected