43.7.13 ADC Digital Comparator Control Register

Table 43-18. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—


Bit	31	30	29	28	27	26	25	24
			IEHIHI	IEHILO	ADCMPHI[11:8]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	ADCMPHI[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	IEBTWN	IELOHI	IELOLO	CMPEN	ADCMPLO[11:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ADCMPLO[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 29 – IEHIHI Enable Comparison - High Limit, Active High

Setting this bit enables comparison events ADCMPHI≤ ADC value.

Note:

This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
The Digital Comparator works on the final value of the filter data.
When using channel using FRACT (16bits left justified) the lower 4 bits are ‘0, therefor in this mode 15:4 will be in 11:0 and user must account for the lower 4 bits of 0’s.
In any case where the results value is of greater resolution than 12 bits, the comparison is only performed on upper 12 bits of the results value according to the settings of register CMPCTRLn.

Bit 28 – IEHILO Enable Comparison - High Limit, Active Low

Setting this bit enables comparison events ADC value < ADCMPHI.

Note:

This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
The Digital Comparator works on the final value of the filter data.
When using channel using FRACT (16bits left justified) the lower 4 bits are ‘0, therefor in this mode 15:4 will be in 11:0 and user must account for the lower 4 bits of 0’s.
In any case where the results value is of greater resolution than 12 bits, the comparison is only performed on upper 12 bits of the results value according to the settings of register CMPCTRLn.

Bits 27:16 – ADCMPHI[11:0] High limit of Digital Analog Comparator n

This register stores the limit value which is used for comparisons with the ADC Module output data when

IEHIHI = 1, IEHILO = 1, or IEBTWN = 1.

The user is responsible for formatting the data in ADCMPHI[11:0] as signed or unsigned to match the data format as specified by the CHNCFG3n.SIGNk and CHNCFG2n.FRACTk bits for all the analog input channels k which are enabled by CHNCFG1n.CHNCMPENk .

Note: In Filter accumulation mode, the comparison is done on the upper 12 of the 16 bits of filter data.

Note:

This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
The Digital Comparator works on the final value of the filter data.
When using channel using FRACT (16bits left justified) the lower 4 bits are ‘0, therefor in this mode 15:4 will be in 11:0 and user must account for the lower 4 bits of 0’s.
In any case where the results value is of greater resolution than 12 bits, the comparison is only performed on upper 12 bits of the results value according to the settings of register CMPCTRLn.

Bit 15 – IEBTWN Enable Comparison - Active Between Limits

Setting this bit enables comparison events ADCMPLO ≤ ADC Value < ADCMPHI.

Note:

This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
The Digital Comparator works on the final value of the filter data.
When using channel using FRACT (16bits left justified) the lower 4 bits are ‘0, therefor in this mode 15:4 will be in 11:0 and user must account for the lower 4 bits of 0’s.
In any case where the results value is of greater resolution than 12 bits, the comparison is only performed on upper 12 bits of the results value according to the settings of register CMPCTRLn.

Bit 14 – IELOHI Enable Comparison - Low Limit, Active High

Setting this bit enables comparison events ADCMPLO≤ ADC Value.

Note:

This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
The Digital Comparator works on the final value of the filter data.
When using channel using FRACT (16bits left justified) the lower 4 bits are ‘0, therefor in this mode 15:4 will be in 11:0 and user must account for the lower 4 bits of 0’s.
In any case where the results value is of greater resolution than 12 bits, the comparison is only performed on upper 12 bits of the results value according to the settings of register CMPCTRLn.

Value	Description
0	Use normal interrupts
1	use early interrupts

Bit 13 – IELOLO Enable Comparison - Low Limit, Active Low

Setting this bit enables comparison events ADC Value < ADCMPLO.

Note:

This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
The Digital Comparator works on the final value of the filter data.
When using channel using FRACT (16bits left justified) the lower 4 bits are ‘0, therefor in this mode 15:4 will be in 11:0 and user must account for the lower 4 bits of 0’s.
In any case where the results value is of greater resolution than 12 bits, the comparison is only performed on upper 12 bits of the results value according to the settings of register CMPCTRLn.

Bit 12 – CMPEN Digital Comparator n Enable

Setting this bit enables digital comparisons for the inputs to ADCn.

For each channel input channel k to ADCn to be compared the corresponding bit CHNCFG1n.CHNCMPENk must be set for the channel to be monitored.

Note:

This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
The Digital Comparator works on the final value of the filter data.
When using channel using FRACT (16bits left justified) the lower 4 bits are ‘0, therefor in this mode 15:4 will be in 11:0 and user must account for the lower 4 bits of 0’s.
In any case where the results value is of greater resolution than 12 bits, the comparison is only performed on upper 12 bits of the results value according to the settings of register CMPCTRLn.

Bits 11:0 – ADCMPLO[11:0] Low limit of Digital Analog Comparator

This register stores the limit value which is used for comparisons with the ADC Module output data when

IELOHI = 1, IELOLO = 1, or IEBTWN = 1.

The user is responsible for formatting the data in ADCMPLO[11:0] as signed or unsigned to match the data format as specified by the CHNCFG3n.SIGNk and CHNCFG2n.FRACTk bits for all the analog input channels k which are enabled by CHNCFG1n.CHNCMPENk .

Note: In Filter accumulation mode, the comparison is done on the upper 12 of the 16 bits of filter data.

Note:

This bit is Enabled Protected : (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
The Digital Comparator works on the final value of the filter data.
When using channel using FRACT (16bits left justified) the lower 4 bits are ‘0, therefor in this mode 15:4 will be in 11:0 and user must account for the lower 4 bits of 0’s.
In any case where the results value is of greater resolution than 12 bits, the comparison is only performed on upper 12 bits of the results value according to the settings of register CMPCTRLn.

Name:	CMPCTRL
Offset:	0xB0
Reset:	0x00000000
Property:	PAC Write-Protected, Enable-Protected