43.7.4 ADC Control Register D

Table 43-9. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CTRLD
Offset:	0x10
Reset:	0x00000000
Property:	Write-Protected, Enable-Protected


Bit	31	30	29	28	27	26	25	24
		VREFSEL[2:0]			WKUPCLKCNT[3:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
				ANLEN				CHNEN
Access				R/W				R/W
Reset				0				0


Bit	15	14	13	12	11	10	9	8
			CTLCKDIV[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0

Access
Reset

Bits 30:28 – VREFSEL[2:0] VREF Input Selection


VREFSEL[2:0]	ADREF+	ADREF-
`000`	A_VDD	A_VSS
`001`	External V_REFH	A_VSS
`010-111`	Reserved	Reserved

Note:

This bit is Enabled Protected. Writes are ignored when CTRLA.ENABLE = 1 and return a bus error.

Bits 27:24 – WKUPCLKCNT[3:0] Wake-Up TAD Clock Count bits

These bits represent the number of ADC TAD clocks required to warm-up the ADC module before it can perform conversion. Although the clocks are specific to each ADC, the WKUPCLKCNT bit is common to all ADC modules.

1111 = 215 = 32,768 TAD clocks

* * *

0110 = 26 = 64 TAD clocks

0101 = 25 = 32 TAD clocks

0100 = 24 = 16 TAD clocks

0011 = 24 = 16 TAD clocks

0010 = 24 = 16 TAD clocks

0001 = 24 = 16 TAD clocks

0000 = 24 = 16 TAD clocks

Note:

Minimum required ADC warm-up time, (i.e., WKUPCLKCNT), is 50 μs. (i.e., TAD * WKUPCLKCNT).
TAD = [1 / ((GCLK_ADC Freq / (CTRLD.CTLCKDIV+1)) / (2 * CORCTRL.ADCDIV)) ] or
(GCLK_ADC Period * (CTRLD.CTLCKDIV+1)) * (2 * ADCDIV).
These bits are Enabled Protected. Writes are ignored when CTRLA.ENABLE = 1 and return a bus error.

Bit 20 – ANLEN Analog and Bias Circuitry Enable for the ADC Module

Note:

The CALCTRL register must be initialized by the users software to the factory-provided values in the CAL OTP Register FCCFG65 before setting ANLEN=1.
CTRLA.ANAEN=1 must be set prior to setting ANLEN=1.
This bit is Enabled Protected. Writes are ignored when CTRLA.ENABLE = 1 and return a bus error.

Value	Description
0	ADC Analog and bias circuitry powered down and clocks suspended. Analog logic power saving mode.
1	Analog and bias circuitry enabled. Once the analog and bias circuit is enabled CTRLA.ANLEN=1 and ANLEN, the ADC module needs a warm-up time, as defined by the WKUPCLKCNT<3:0> bits.

Bit 16 – CHNEN ADC Module Digital Enable

Note:

This bit is Enabled Protected. Writes are ignored when CTRLA.ENABLE = 1 and return a bus error.
ANLEN qualifies CHNEN: If ANLEN =0, then digital logic is also disabled.

Value	Description
0	ADC digital logic disabled. No trigger, sample or conversion events will be processed. (power-saving mode with fast 2 TAD clock wakeup provided ANLEN = 1).
1	ADC digital logic enabled (required for active operation).

Bits 13:8 – CTLCKDIV[5:0] A/D Clock Source to Control Clock Divider

The CTLCKDIV bit field divides the GCLK_ADC input clock into the ADC Module control clock CTL_CLK scaled by CTRLD.CTLCKDIV with period T_Q.

Note: This bit is Enabled Protected. Writes are ignored when CTRLA.ENABLE = 1 and returns a bus error.

Value	Description
111111	T_{GCLK_ADCx}·(CTLCKDIV[5:0]+1) = 64·T_{GCLK_ADCx} = T_Q
111110	T_{GCLK_ADCx}·(CTLCKDIV[5:0]+1) = 63·T_{GCLK_ADCx} = T_Q
...	...
000100	T_{GCLK_ADCx}·(CTLCKDIV[5:0]+1) = 5·T_{GCLK_ADCx} = T_Q
000011	T_{GCLK_ADCx}·(CTLCKDIV[5:0]+1) = 4·T_{GCLK_ADCx} = T_Q
000010	T_{GCLK_ADCx}·(CTLCKDIV[5:0]+1) = 3·T_{GCLK_ADCx} = T_Q
000001	T_{GCLK_ADCx}·(CTLCKDIV[5:0]+1) = 2·T_{GCLK_ADCx} = T_Q
000000	T_{GCLK_ADCx}·(CTLCKDIV[5:0]+1) = 1·T_{GCLK_ADCx} = T_Q