1.8.1 MDDR/FDDR Impedance Calibration

The MDDR and FDDR have a DDRIO calibration block. DDRIO can use fixed impedance calibration for different drive strengths, and these values can be programmed using the Libero SoC software for the selected I/O standard.

Before initiating DDRIO impedance calibration, either of the following must be performed.

• Power sequencing, where the DDRIO bank VDDIx supply must be up and stable before VDD core supply.
• DDRIO re-calibration through the APB interface after DDRIO-VDDIx and VDD are up and stable.

For more information on impedance calibration, see the UG0445: SmartFusion2 SoC FPGA and IGLOO2 FPGA Fabric User Guide .