36.7.4 MPDDRC Timing Parameter 0 Register

This register can only be written if the WPEN bit is cleared in the MPDDRC Write Protection Mode Register.

Name: MPDDRC_TPR0
Offset: 0x0C
Reset: 0x20227225
Property: Read/Write

Bit 3130292827262524 
 TMRD[3:0] TWTR[2:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0010000 
Bit 2322212019181716 
 TRRD[3:0]TRP[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00100010 
Bit 15141312111098 
 TRC[3:0]TWR[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 01110010 
Bit 76543210 
 TRCD[3:0]TRAS[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00100101 

Bits 31:28 – TMRD[3:0] Load Mode Register Command to Activate or Refresh Command

This field defines the delay between a Load mode register command and an Activate or Refresh command in number of DDRCK clock cycles. The number of cycles is between 0 and 15. For low-power DDR2-SDRAM and low-power DDR3-SDRAM, this field is equivalent to tMRW.

Bits 26:24 – TWTR[2:0] Internal Write to Read Delay

This field defines the internal Write to Read command time in number of DDRCK clock cycles. The number of cycles is between 1 and 7.

Bits 23:20 – TRRD[3:0] Active BankA to Active BankB

This field defines the delay between an Activate command in BankA and an Activate command in BankB in number of DDRCK clock cycles. The number of cycles is between 1 and 15.

Bits 19:16 – TRP[3:0] Row Precharge Delay

This field defines the delay between a Precharge command and another command in number of DDRCK clock cycles. The number of cycles is between 0 and 15.

Bits 15:12 – TRC[3:0] Row Cycle Delay

This field defines the delay between an Activate command and a Refresh command in number of DDRCK clock cycles. The number of cycles is between 0 and 15.

Bits 11:8 – TWR[3:0] Write Recovery Delay

This field defines the Write Recovery Time in number of DDRCK clock cycles. The number of cycles is between 1 and 15.

Bits 7:4 – TRCD[3:0] Row to Column Delay

This field defines the delay between an Activate command and a Read/Write command in number of DDRCK clock cycles. The number of cycles is between 0 and 15.

Bits 3:0 – TRAS[3:0] Active to Precharge Delay

This field defines the delay between an Activate command and a Precharge command in number of DDRCK clock cycles. The number of cycles is between 0 and 15.