Shifts the sampling point of data coming from the memory device. The
higher the memory device clock frequency, the higher the SHIFT_SAMPLING value. Refer
to the section "Electrical Characteristics".
In the case of DDR3-SDRAM devices, the field
SHIFT_SAMPLING must be set to 2, and the field CAS must be set to 5. See “CAS: CAS
Latency” in MPDDRC_CR.
| Value | Name | Description |
|---|
| 0 |
NO_SHIFT |
Initial
sampling point. |
| 1 |
SHIFT_ONE_CYCLE |
Sampling
point is shifted by one cycle. |
| 2 |
SHIFT_TWO_CYCLES |
Sampling
point is shifted by two cycles. |
| 3 |
SHIFT_THREE_CYCLES |
Sampling
point is shifted by three cycles, unique for LPDDR2,
DDR3 and LPDDR3. Not applicable
for DDR2 and LPDDR1 devices. |
