36.7.6 MPDDRC Timing Parameter 2 Register

Name: MPDDRC_TPR2
Offset: 0x14
Reset: 0x00042062
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     TFAW[3:0] 
Access R/WR/WR/WR/W 
Reset 0100 
Bit 15141312111098 
  TRTP[2:0]TRPA[3:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0100000 
Bit 76543210 
 TXARDS[3:0]TXARD[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 01100010 

Bits 19:16 – TFAW[3:0] Four Active Windows

DDR2 and DDR3 devices with eight banks (1 Gbit or larger) have an additional requirement concerning tFAW timing. This requires that no more than four Activate commands may be issued in any given tFAW (MIN) period.

The number of cycles is between 0 and 15.

This field is found only in DDR2-SDRAM, LPDDR2-SDRAM, DDR3-SDRAM and LPDDR3-SDRAM devices.

Bits 14:12 – TRTP[2:0] Read to Precharge

Defines the delay between a Read command and a Precharge command in number of DDRCK clock cycles.

The number of cycles is between 0 and 7.

Bits 11:8 – TRPA[3:0] Row Precharge All Delay

Defines the delay between a Precharge All Banks command and another command in number of DDRCK clock cycles. The number of cycles is between 0 and 15.

This field is found only in the DDR2-SDRAM devices.

In the case of LPDDR2-SDRAM and LPDDR3-SDRAM, this field is equivalent to tRPAB.

Bits 7:4 – TXARDS[3:0] Exit Active Power Down Delay to Read Command in Mode “Slow Exit”

Defines the delay between CKE set high and a Read command in number of DDRCK clock cycles. The number of cycles is between 0 and 15.

This field is found only in the DDR2-SDRAM devices.

Bits 3:0 – TXARD[3:0] Exit Active Power Down Delay to Read Command in Mode “Fast Exit”

Defines the delay between CKE set high and a Read command in number of DDRCK clock cycles. The number of cycles is between 0 and 15.

This field is found only in the DDR2-SDRAM devices.