36.7.7 MPDDRC Low-Power Register


Bit	31	30	29	28	27	26	25	24
							SELF_DONE	CHG_FRQ
Access							R	R/W
Reset							0	0


Bit	23	22	21	20	19	18	17	16
			UPD_MR[1:0]					APDE
Access			R/W	R/W				R/W
Reset			0	0				1


Bit	15	14	13	12	11	10	9	8
			TIMEOUT[1:0]			DS[2:0]
Access			R/W	R/W		R/W	R/W	R/W
Reset			0	0		0	0	0


Bit	7	6	5	4	3	2	1	0
		PASR[2:0]			LPDDR2_LPDDR3_PWOFF	CLK_FR	LPCB[1:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0

Bit 25 – SELF_DONE Self-Refresh is Done

Indicates that external device is in Self-refresh mode.

Bit 24 – CHG_FRQ Change Clock Frequency During Self-Refresh Mode

This mode is used to change the low-power DDR-DRAM or DDR3-SDRAM input clock frequency. This mode is unique to the low-power DDR-DRAM and DDR3-SDRAM devices.

Bits 21:20 – UPD_MR[1:0] Update Load Mode Register and Extended Mode Register

Used to enable or disable automatic update of the Load Mode register and Extended Mode register. This update depends on the MPDDRC integration in a system. The MPDDRC can either share or not an external bus with another controller.

Value	Name	Description
0	NO_UPDATE	Update of Load Mode and Extended Mode registers is disabled.
1	UPDATE_SHAREDBUS	The MPDDRC shares an external bus. Automatic update is done during a refresh command and a pending read or write access in the SDRAM device.
2	UPDATE_NOSHAREDBUS	The MPDDRC does not share an external bus. Automatic update is done before entering Self-refresh mode.
3	–	Reserved

Bit 16 – APDE Active Power Down Exit Time

This mode is unique to the DDR2-SDRAM and DDR3-SDRAM devices.

This mode manages the active Power-down mode which determines performance versus power saving.

After the initialization sequence, as soon as the APDE field is modified, the Extended Mode register (located in the memory of the external device) is accessed automatically and APDE bits are updated. Depending on the UPD_MR bit, update is done before entering Self-refresh mode or during a refresh command and a pending read or write access

Value	Name	Description
0	DDR2_FAST_EXIT	Fast exit from power-down. DDR2-SDRAM and DDR3-SDRAM devices only.
1	DDR2_SLOW_EXIT	Slow exit from power-down. DDR2-SDRAM and DDR3-SDRAM devices only.

Bits 13:12 – TIMEOUT[1:0] Time Between Last Transfer and Low-Power Mode

Defines when Low-power mode is activated.

Value	Name	Description
0	NONE	SDRAM Low-power mode is activated immediately after the end of the last transfer.
1	DELAY_64_CLK	SDRAM Low-power mode is activated 64 clock cycles after the end of the last transfer.
2	DELAY_128_CLK	SDRAM Low-power mode is activated 128 clock cycles after the end of the last transfer.
3	–	Reserved

Bits 10:8 – DS[2:0] Drive Strength

Unique to low-power DDR1-SDRAM. Selects the output drive strength.

After the initialization sequence, as soon as the DS field is modified, the Extended Mode Register is accessed automatically and DS bits are updated. Depending on the UPD_MR bit, update is done before entering Self-refresh mode or during a refresh command and a pending read or write access.

Value	Name	Description
0	DS_FULL	Full drive strength
1	DS_HALF	Half drive strength
2	DS_QUARTER	Quarter drive strength
3	DS_OCTANT	Octant drive strength
4–7	–	Reserved

Bits 6:4 – PASR[2:0] Partial Array Self-Refresh

Is unique to low-power DDR1-SDRAM. Used to specify whether only one-quarter, one-half or all banks of the DDR-SDRAM array are enabled. Disabled banks are not refreshed in Self-refresh mode.

The values of this field are dependent on the low-power DDR-SDRAM devices.

After the initialization sequence, as soon as the PASR field is modified, the Extended Mode Register in the external device memory is accessed automatically and PASR bits are updated. Depending on the UPD_MR bit, update is done before entering Self-refresh mode or during a refresh command and a pending read or write access.

Bit 3 – LPDDR2_LPDDR3_PWOFF LPDDR2/3 Power Off Bit

The LPDDR2/3 power-off sequence must be controlled to preserve the LPDDR2/3 device. The power failure is handled at system level (IRQ or FIQ) and the LPDDR2/3 power-off sequence is applied using LPDDR2_LPDDR3_PWOFF.

LPDDR2_LPDDR3_PWOFF is used to force CKE low before a power-off sequence. Uncontrolled power-off sequences can be applied only up to 400 times in the life of an LPDDR2/3 device.

Value	Name	Description
0	DISABLED	No power-off sequence applied to LPDDR2/3.
1	ENABLED	A power-off sequence is applied to the LPDDR2/3 device. CKE is forced low.

Bit 2 – CLK_FR Clock Frozen Command Bit

Sets the clock low during Power-down mode. Some DDR-SDRAM devices do not support freezing the clock during Power-down mode. Refer to the relevant DDR-SDRAM device data sheet for details.

Value	Name	Description
0	DISABLED	Clock(s) is/are not frozen.
1	ENABLED	Clock(s) is/are frozen.

Bits 1:0 – LPCB[1:0] Low-power Command Bit

Value	Name	Description
0	NOLOWPOWER	Low-power feature is inhibited. No Power-down, Self-refresh and Deep power modes are issued to the DDR-SDRAM device.
1	SELFREFRESH	The MPDDRC issues a self-refresh command to the DDR-SDRAM device, the clock(s) is/are deactivated and the CKE signal is set low. The DDR-SDRAM device leaves the Self-refresh mode when accessed and reenters it after the access.
2	POWERDOWN	The MPDDRC issues a Power-down command to the DDR-SDRAM device after each access, the CKE signal is set low. The DDR-SDRAM device leaves the Power-down mode when accessed and reenters it after the access.
3	DEEPPOWERDOWN	The MPDDRC issues a Deep Power-down command to the low-power DDR-SDRAM device.

Name:	MPDDRC_LPR
Offset:	0x1C
Reset:	0x00010000
Property:	Read/Write