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Audio Recording and Playback Using Direct Memory Access and Core Independent Peripherals AN3548
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PIC18F57Q43
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5
Application Setup
5.6
DMA Setup
AN3548
Introduction
1
Theory of Operation
2
Memory Organization
3
Data Transfer Operations
4
Switch Debouncing
5
Application Setup
5.1
CPU Setup
5.2
TMR0 Setup
5.3
ADCC Setup
5.4
DAC1 Setup
5.5
SPI1 Setup
5.6
DMA Setup
5.7
PWM1 Setup
5.8
CMP1 Setup
5.9
TMR2/4 Setup
5.10
CLC1/2 Setup
5.11
TMR6 Setup
5.12
TMR1 Setup
5.13
UART1 Setup
6
Software Implementation
7
Hardware Implementation
8
Conclusion
9
References
10
Revision History
The Microchip Website
Product Change Notification Service
Customer Support
Microchip Devices Code Protection Feature
Legal Notice
Trademarks
Quality Management System
Worldwide Sales and Service
5.6 DMA Setup
See
Data Transfer Operations
for DMA setups for various data transfer operations.
