26.5 Interrupts

The Timer1 module has the ability to generate an interrupt on a period match or falling edge of the external gate signal, depending on the operating mode.

The TxIF bit is set when one of the following conditions is true:

• When the TMRx count matches the respective PRx register and the Timer module is not operating in Gated Time Accumulation mode
• When the falling edge of the gate signal is detected while the Timer is operating in Gated Time Accumulation mode

The TxIF bit must be cleared in software.

The Timer module is enabled as a source of interrupt via the Timer Interrupt Enable bit, TxIE. The Timer Interrupt Priority Level bits, TxIP[2:0], define the priority group to which the interrupt source will be assigned.