11.6 Peripheral Access Controller (PAC)

Legacy devices used a locking mechanism where the user wrote 0xAA and 0x55 into NVMKEY in a sequence. This was to prevent accidental enabling or disabling of critical peripherals. This feature has been replaced with a dedicated module called the PAC.

Register Locking and Unlocking

The module implements an OR gate between the associated peripheral’s PACCONx lock bit and the inverse of the PACCONx write enable bit. See Figure 11-2 for a diagram of the PAC locking behavior. If the target peripheral LK bit or the inverse of the WR bit is set, the target register or registers cannot be written to, only read access is allowed. Also, whenever the LK or WR bit in PACCON is set or cleared, a minimum of two cycles is required for the lock or unlock to take effect.

At device reset, all WR bits are set to '1' and all LK bits are set to '0'. This means that writes to all peripheral registers are allowed. The user can then configure access to the peripherals using the WR and LK bits. Please note that LK bits are 'One Way Settable' and will remain set until next device reset and cannot be cleared in software.

Individual and Range Mode

The PAC module can lock/unlock individual registers and lock/unlock a range of registers depending on which registers are the target registers. If the PAC module uses range mode, the entire range of target peripheral registers is covered by that lock and write enable bit. Table 11-12 below is used to determine which registers use individual or range mode.