40.2 AC Characteristics and Timing Parameters

Figure 40-1. Load Condition for Device Timing Specifications
Table 40-22. Capacitive Loading Requirements on Output Pins
Param
 No.SymbolCharacteristicMin.Typ.Max.UnitsConditions
DO50COSCOOSCO Pin——20pFIn XT and HS modes, when External Clock is used to drive OSCI
DO56CIOAll I/O Pins and OSCO——20pFEC mode
DO58CBSCLx, SDAx——400pFIn I2C mode
Figure 40-2. External Clock Timing
Table 40-23. External Clock Timing Requirements

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymCharacteristicMin.Typ.(1)Max.UnitsConditions
OS10FINExternal CLKI Frequency (External Clocks allowed only
 in EC mode)DC—64MHzEC
Oscillator Crystal Frequency3.5—10MHzXT
10—32MHzHS
OS11FREFIREFI External Clock Input——50MHz
OS20TOSCTOSC = 1/FOSC15.6——ns
OS25TCYInstruction Cycle Time5—DCns
OS30TOSL,

TOSH

External Clock in (OSCI)
High or Low Time0.45 x TOSC—0.55 x TOSCnsEC
OS40TCKRCLKO Rise Time———nsRefer to DO31
OS41TCKFCLKO Fall Time———nsRefer to DO32
OS42GMExternal Oscillator 
Transconductance(3)2.8—3.7mA/VPXTALCFG[1:0] = 00, PXTALCFG[2] = 0
4.5—6.2mA/VPXTALCFG[1:0] = 00, PXTALCFG[2] = 1
4.5—6.2mA/VPXTALCFG[1:0] = 01, PXTALCFG[2] = 0
7—10.5mA/VPXTALCFG[1:0] = 01, PXTALCFG[2] = 1
5.8—8.5mA/VPXTALCFG[1:0] = 10, PXTALCFG[2] = 0
8.9—14.1mA/VPXTALCFG[1:0] = 10, PXTALCFG[2] = 1
7—10.5mA/VPXTALCFG[1:0] = 11, PXTALCFG[2] = 0
10.7—17.3mA/VPXTALCFG[1:0] = 11, PXTALCFG[2] = 1
Note:
  1. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  2. Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin.
  3. Parameters characterized but not tested in manufacturing.
Table 40-24. PLLn Timing Specifications(1)

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristicMin.Typ.(1)Max.UnitsConditions
OS50FPLLIPLL Voltage Controlled Oscillator (VCO) Input Frequency Range5—64MHz
OS51FVCOOn-Chip VCO System Frequency500—1600MHz
OS52MFeedback Divider Value16—400N/A
OS53TLOCKPLL Start-up Time (Lock Time)(2)—125188µsFPLLI = 8 MHz
OS54DCLKCLKO Stability (Jitter)—1—psFVCO = 1600 MHz, FOUT = 400 MHz
OS55FOUT PLL PostDiv Output——800MHz
OS56FOUTDIVPLL VCO FractDiv Output——800MHz
OS57FINDIVPLL FracDiv Input,500—800MHz
Note:
  1. Parameters for design guidance only and not tested in manufacturing.
  2. Parameters characterized but not tested in manufacturing.
Table 40-25. Peripheral Input Clock Timing Specifications(1)

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

CharacteristicMin.Max.UnitsConditions
FINMAXCLKGEN0800MHzCLKGEN input
PWM0400MHz
ADC32320MHz
DAC400500MHz
DMT—200MHz
MCCP0200MHzSystem clock
SPI0320MHz
UART0320MHz
PTG0400MHzFrom PWM clock
0320MHzFrom ADC clock
CLC0200MHzSystem clock
I2C0100MHzStandard speed clock
SENT0100MHzStandard speed clock
BISS0320MHz
CRC0200MHzFast speed clock
QEI0100MHzStandard speed clock
QEI0100MHzStandard speed clock
PPS050MHzSlow speed clock
GPIO0200MHzFast speed clock for PORTx and LATx registers
050MHzSlow Speed clock, all other GPIO registers
JTAG020MHzTCK max input clock
Note:

  1. Parameters are for design guidance only and are not tested.

Table 40-26. Internal FRC Accuracy

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param No.CharacteristicMin.Max.UnitsConditions
Internal FRC Accuracy @ FRC Frequency = 8 MHz(1)
F20FRC-1.51.5%-40°C ≤ TA ≤ 85°C
-22%+85°C ≤ TA ≤ +125°C
F21BFRC-22%-40°C ≤ TA ≤ +125°C
F22BFRC/244-LPRC-33%-40°C ≤ TA ≤ +125°C
Note:
  1. Frequency is calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift.
Figure 40-3. I/O Timing Characteristics
Table 40-27. I/O Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristicMin.Typ.(1)Max.UnitsConditions
DO31TIORPort Output Rise Time(2)—3.24ns4x output pins
—2.33.1ns8x output pins
DO32TIOFPort Output Fall Time(2)—2.53ns4x output pins
—1.72.4ns8x output pins
DO33FREFOREFO Output Frequency——30MHz
DI35TINPINTx Pin High or Low Time (input)6——ns
DI40TRBPCNx High or Low Time (input)2——TCY
Note:
  1. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  2. Parameters characterized but not tested in manufacturing.
Figure 40-4. BOR and Master Clear Reset Timing Characteristics
Table 40-28. Reset and Watchdog Timer Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param
 No.SymbolCharacteristic(1)Min.Typ.Max.UnitsConditions
SY00TPUPower-up Period—80—µsBOR trip point to first instruction on FRC
SY13TIOZI/O High-Impedance from MCLR Low or Watchdog Timer Reset—1—µs
SY20TMCLRMCLR Pulse Width (low)8——µs
SY35TFSCMFail-Safe Clock Monitor Delay——2µsClock fail to BFRC ready
SY40FMINFail-Safe Clock Monitor Minimum Frequency4——MHz
Note:
  1. Parameters characterized but not tested in manufacturing.
Figure 40-5. High-Speed PWMx Module Fault Timing Characteristics
Figure 40-6. High-Speed PWMx Module Timing Characteristics
Table 40-29. High-Speed PWMx Module Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param
No.SymbolCharacteristicMin.Typ.Max.UnitsConditions
MP10TFPWMPWMx Output Fall Time———nsSee Parameter DO32
MP11TRPWMPWMx Output Rise Time———nsSee Parameter DO31
MP20TFDFault Input ↓ to PWMx

I/O Change(1)

—15—nsPCI Inputs 19 through 22, level triggered
MP30TFHFault Input Pulse Width(1)4——ns
Note:
  1. These parameters are characterized but not tested in manufacturing.
Figure 40-7. QEI Module Index Pulse Timing Characteristics
Table 40-30. QEI Index Pulse Timing Requirements

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param
No.SymbolCharacteristic(1)Min.MaxUnitsConditions
TQ50TqILFilter Time to Recognize Low with Digital Filter(2)3 * N * TCY—nsN = 1, 2, 4, 16, 32, 64, 128 and 256
TQ51TqiHFilter Time to Recognize High with Digital Filter(2)3 * N * TCY—nsN = 1, 2, 4, 16, 32, 64, 128 and 256
TQ55TqidxrIndex Pulse Recognized to Position Counter Reset (ungated index)3 TCY—ns
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Alignment of index pulses to QEIA and QEIB is shown for Position Counter Reset timing only. Shown for forward direction only (QEIA leads QEIB). Same timing applies for reverse direction (QEIA lags QEIB), but index pulse recognition occurs on the falling edge.
Table 40-31. SPIx Maximum Data/Clock Rate Summary

SPI Host

Transmit Only

(Half-Duplex)

SPI Host

Transmit/

Receive

(Full-Duplex)

SPI Client

Transmit/

Receive

(Full-Duplex)

CKE

Maximum

Data Rate (MHz)

Condition

Figure 40-8
Figure 40-9——025Using PPS
50Dedicated Pin
Figure 40-9
Table 40-32——125Using PPS
50Dedicated Pin
—Figure 40-10
Table 40-33—025Using PPS
50Dedicated Pin
—Figure 40-11
Table 40-34—125Using PPS
50Dedicated Pin
——Figure 40-12
Table 40-35025Using PPS
50Dedicated Pin
——Figure 40-13
Table 40-36125Using PPS
50Dedicated Pin
Figure 40-8. SPIx Host Mode (Half-Duplex, Transmit Only, CKE = 0) 
Timing Characteristics
Figure 40-9. SPIx Host Mode (Half-Duplex, Transmit Only, CKE = 1) 
Timing Characteristics
Table 40-32. SPIx Host Mode (Half-Duplex, Transmit Only) Timing Requirements(1)

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param
No.SymbolCharacteristicMin.Typ.(2)Max.UnitsConditions
SP10FSCPMaximum SCKx Frequency——25MHzUsing PPS pins
——50MHzSPI2 dedicated pins
SP20TSCFSCKx Output Fall Time(3)——5nsUsing PPS pins
——2.5SPI2 dedicated pins
SP21TSCRSCKx Output Rise Time(3)——6nsUsing PPS pins
——3.1nsSPI2 dedicated pins
SP30TDOF(3)SDOx Data Output Fall Time——5nsUsing PPS pins
——2.5nsSPI2 dedicated pins
SP31TDOR(3)SDOx Data Output Rise Time——6nsUsing PPS pins
——3.1nsSPI2 dedicated pins
SP35TSCH2DOV,
TSCL2DOVSDOx Data Output Valid After SCKx Edge——7nsUsing PPS pins
2.7—4.4nsSPI dedicated pins
SP36TDIV2SCH,
TDIV2SCLSDOx Data Output Setup to First SCKx Edge10——nsUsing PPS pins
1—2nsSPI2 dedicated pins
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  3. Assumes 30 pF load on all SPIx pins.
Figure 40-10. SPIx Host Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) 
Timing Characteristics
Table 40-33. SPIx Host Mode (Full-Duplex, CKE = 1, CKP = X, SMP = 1) 
Timing Requirements(1)

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristicMin.Typ.(2)Max.UnitsConditions
SP10FSCPMaximum SCKx Frequency——25MHzUsing PPS pins
——50MHzSPI2 dedicated pins
SP20TSCFSCKx Output Fall Time(3)——5nsUsing PPS pins
——2.5nsSPI2 dedicated pins
SP21TSCRSCKx Output Rise Time(3)——6nsUsing PPS pins
——3.1nsSPI2 dedicated pins
SP30TDOFSDOx Data Output Fall Time(3)——5nsUsing PPS pins
——2.5nsSPI2 dedicated pins
SP31TDORSDOx Data Output Rise Time(3)——6nsUsing PPS pins
——3.1nsSPI2 dedicated pins
SP35TSCH2DOV,

TSCL2DOV

SDOx Data Output Valid After SCKx Edge——7nsUsing PPS pins
2.7—4.4nsSPI2 dedicated pins
SP36TDOV2SC, TDOV2SCLSDOx Data Output Setup to First SCKx Edge10——nsUsing PPS pins
1—2nsSPI2 dedicated pins
SP40TDIV2SCH, TDIV2SCLSetup Time of SDIx Data Input to SCKx Edge——17nsUsing PPS pins
0.1—0.6nsSPI2 dedicated pins
SP41TSCH2DIL, TSCL2DILHold Time of SDIx Data Input to SCKx Edge2——nsUsing PPS pins
2.5—3.3nsSPI2 dedicated pins
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  3. Assumes 30 pF load on all SPIx pins.
Figure 40-11. SPIx Host Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) 
Timing Characteristics
Table 40-34. SPIx Host Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) 
Timing Requirements(1)

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param
No.SymbolCharacteristicMin.Typ.(2)Max.UnitsConditions
SP10FSCPMaximum SCKx Frequency——25MHzUsing PPS pins
——50MHzSPI2 dedicated pins
SP20TSCFSCKx Output Fall Time(3)——5nsUsing PPS pins
——2.5nsSPI2 dedicated pins
SP21TSCRSCKx Output Rise Time(3)——6nsUsing PPS pins
——3.1nsSPI2 dedicated pins
SP30TDOFSDOx Data Output Fall Time(3)——5nsUsing PPS pins
——2.5nsSPI2 dedicated pins
SP31TDORSDOx Data Output Rise Time(3)——6nsUsing PPS pins
——3.1nsSPI2 dedicated pins
SP35TSCH2DOV,

TSCL2DOV

SDOx Data Output Valid After SCKx Edge——7nsUsing PPS pins
2.7—4.4nsSPI2 dedicated pins
SP40TdiV2SCH, TdiV2SCLSetup Time of SDIx Data Input to SCKx Edge——17nsUsing PPS pins
0.1—0.6nsSPI2 dedicated pins
SP41TSCH2DIL, TSCL2DILHold Time of SDIx Data Input
 to SCKx Edge2——nsUsing PPS pins
2.5—3.3nsSPI2 dedicated pins
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  3. Assumes 30 pF load on all SPIx pins.
Figure 40-12. SPIx Client Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 0) 
Timing Characteristics
Table 40-35. SPIx Client Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 0) 
Timing Requirements(1)

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolChar.Min.Typ.(2)Max.UnitsConditions
SP10FSCPMaximum SCKx Input Frequency——25MHzUsing PPS pins
——50MHzSPI2 dedicated pins
SP72TSCFSCKx Input Fall Time(3)——5nsUsing PPS pins
——2.5nsSPI2 dedicated pins
SP73TSCRSCKx Input Rise Time(3)——6nsUsing PPS pins
——3.1nsSPI2 dedicated pins
SP30TDOFSDOx Data Output Fall Time(3)——5nsUsing PPS pins
——2.5nsSPI2 dedicated pins
SP31TDORSDOx Data Output Rise Time(3)——6nsUsing PPS pins
——3.1nsSPI2 dedicated pins
SP35TSCH2DOV,

TSCL2DOV

SDOx Data Output Valid After
 SCKx Edge——7nsUsing PPS pins
2.7—4.4nsSPI2 dedicated pins
SP40TDIV2SCH, TDIV2SCLSetup Time of SDIx Data Input
 to SCKx Edge——17nsUsing PPS pins
1—1nsSPI2 dedicated pins
SP41TSCH2DIL, TSCL2DILHold Time of SDIx Data Input
 to SCKx Edge2——nsUsing PPS pins
2.5—3.3nsSPI2 dedicated pins
SP50TSSL2SCH, TSSL2SCLSSx ↓ to SCKx ↑ or SCKx ↓ Input90——ns
SP51TSSH2DOZSSx ↑ to SDOx Output
High-Impedance5—20ns
SP52TSCH2SSH,

TSCL2SSH

SSx ↑ After SCKx Edge(3)1.5 TCY + 40——ns
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  3. Assumes 30 pF load on all SPIx pins.
Figure 40-13. SPIx Client Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 0) 
Timing Characteristics
Table 40-36. SPIx Client Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 0) 
Timing Requirements(1)

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristicMin.Typ.(2)Max.UnitsConditions
SP10FSCPMaximum SCKx Input 
Frequency——25MHzUsing PPS pins
——50MHzSPI2 dedicated pins
SP72TSCFSCKx Input Fall Time(3)——5nsUsing PPS pins
——2.5nsSPI2 dedicated pins
SP73TSCRSCKx Input Rise Time(3)——6nsUsing PPS pins
——3.1nsSPI2 dedicated pins
SP30TDOFSDOx Data Output Fall Time(3)——5nsUsing PPS pins
——2.5nsSPI2 dedicated pins
SP31TDORSDOx Data Output Rise Time(3)——6nsUsing PPS pins
——3.1nsSPI2 dedicated pins
SP35TSCH2DOV,

TSCL2DOV

SDOx Data Output Valid After
 SCKx Edge——7nsUsing PPS pins
2.7—4.4nsSPI dedicated pins
SP40TDIV2SCH, TDIV2SCLSetup Time of SDIx Data Input
 to SCKx Edge——17nsUsing PPS pins
0.1—0.6nsSPI2 dedicated pins
SP41TSCH2diL, TSCL2DILHold Time of SDIx Data Input
 to SCKx Edge2——nsUsing PPS pins
2.5—3.3nsSPI2 dedicated pins
SP50TSSL2SCH, TssL2scLSSx ↓ to SCKx ↑ or SCKx ↓ Input90——ns
SP51TSSH2doZSSx ↑ to SDOx Output
High-Impedance(3)5—20ns
SP52TSCH2SSH,

TSCL2SSH

SSx ↑ After SCKx Edge(3)1.5 TCY + 40——ns
SP60TSSL2DOVSDOx Data Output Valid After SSx Edge——50ns
Note:
  1. These parameters are characterized but not tested in manufacturing.
  2. Data in “Typ.” column are at 3.3V, +25°C unless otherwise stated.
  3. Assumes 30 pF load on all SPIx pins.
Figure 40-14. I2Cx Bus Start/Stop Bits Timing Characteristics (Host Mode)
Figure 40-15. I2Cx Bus Data Timing Characteristics (Host Mode)
Table 40-37. I2Cx Bus Data Timing Requirements (Host Mode)

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristic(4)Min.(1)Max.UnitsConditions
IM10Tlo:sclClock Low Time100 kHz modeTCY (BRG + 1)—µs
400 kHz modeTCY (BRG + 1)—µs
1 MHz mode(2)TCY (BRG + 1)—µs
IM11Thi:sclClock High Time100 kHz modeTCY (BRG + 1)—µs
400 kHz modeTCY (BRG + 1)—µs
1 MHz mode(2)TCY (BRG + 1)—µs
IM20Tf:sclSDAx and SCLx
Fall Time100 kHz mode—300nsCb is specified to be from 10 to 400 pF
400 kHz mode20 x (VDD/5.5V)300ns
1 MHz mode(2)—120ns
IM21Tr:sclSDAx and SCLx
Rise Time100 kHz mode—1000nsCb is specified to be from 10 to 400 pF
400 kHz mode20 + 0.1 Cb300ns
1 MHz mode(2)—120ns
IM25Tsu:datData Input
Setup Time100 kHz mode250—ns
400 kHz mode100—ns
1 MHz mode(2)50—ns
IM26Thd:datData Input
Hold Time100 kHz mode0—µs
400 kHz mode00.9µs
1 MHz mode(2)00.3µs
IM30Tsu:staStart Condition
Setup Time100 kHz modeTCY (BRG + 1)—µsOnly relevant for Repeated Start
condition
400 kHz modeTCY (BRG + 1)—µs
1 MHz mode(2)TCY (BRG + 1)—µs
IM31Thd:staStart Condition Hold Time100 kHz modeTCY (BRG + 1)—µsAfter this period, the
 first clock pulse is
 generated
400 kHz modeTCY (BRG + 1)—µs
1 MHz mode(2)TCY (BRG + 1)—µs
IM33Tsu:stoStop Condition Setup Time100 kHz modeTCY (BRG + 1)—µs
400 kHz modeTCY (BRG + 1)—µs
1 MHz mode(2)TCY (BRG + 1)—µs
IM34Thd:stoStop Condition

Hold Time

100 kHz modeTCY (BRG + 1)—µs
400 kHz modeTCY (BRG + 1)—µs
1 MHz mode(2)TCY (BRG + 1)—µs
IM40Taa:sclOutput Valid from Clock100 kHz mode—3450ns
400 kHz mode—900ns
1 MHz mode(2)—450ns
IM45Tbf:sdaBus Free Time100 kHz mode4.7—µsTime the bus must be free before a new
 transmission can start
400 kHz mode1.3—µs
1 MHz mode(2)0.5—µs
IM50CbBus Capacitive Loading—400pF
IM51TpgdPulse Gobbler Delay(3)65390ns
Note:
  1. BRG is the value of the I2C Baud Rate Generator.
  2. Maximum Pin Capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
  3. Typical value for this parameter is 130 ns.
  4. These parameters are characterized but not tested in manufacturing.
Figure 40-16. I2Cx Bus Start/Stop Bits Timing Characteristics (Client Mode)
Figure 40-17. I2Cx Bus Data Timing Characteristics (Client Mode)
Table 40-38. I2Cx Bus Data Timing Requirements (Client Mode)

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial


-40°C ≤ TA ≤ +125°C for Extended

Param No.SymbolCharacteristic(3)Min.Max.UnitsConditions
IS10Tlo:sclClock Low Time100 kHz mode4.7—µs
400 kHz mode1.3—µs
1 MHz mode(1)0.5—µs
IS11Thi:sclClock High Time100 kHz mode4.0—µsDevice must operate at a minimum of 1.5 MHz
400 kHz mode0.6—µsDevice must operate at a minimum of 10 MHz
1 MHz mode(1)0.28—µs
IS20Tf:sclSDAx and SCLx
Fall Time100 kHz mode—300nsCb is specified to be from
 10 to 400 pF
400 kHz mode20 x (VDD/5.5V)300ns
1 MHz mode(1)20 x (VDD/5.5V)120ns
IS21Tr:sclSDAx and SCLx
Rise Time100 kHz mode20 + 0.1 Cb1000nsCb is specified to be from
 10 to 400 pF
400 kHz mode—300ns
1 MHz mode(1)—120ns
IS25Tsu:datData Input
Setup Time100 kHz mode250—ns
400 kHz mode100—ns
1 MHz mode(1)50—ns
IS26Thd:datData Input
Hold Time100 kHz mode0—µs
400 kHz mode00.9µs
1 MHz mode(1)00.3µs
IS30Tsu:staStart Condition
Setup Time100 kHz mode4.7—µsOnly relevant for Repeated Start condition
400 kHz mode0.6—µs
1 MHz mode(1)0.26—µs
IS31Thd:staStart Condition Hold Time100 kHz mode4.0—µsAfter this period, the first clock pulse is generated
400 kHz mode0.6—µs
1 MHz mode(1)0.26—µs
IS33Tsu:stoStop Condition Setup Time100 kHz mode4—µs
400 kHz mode0.6—µs
1 MHz mode(1)0.26—µs
IS34Thd:stoStop Condition

Hold Time

100 kHz mode> 0—µs
400 kHz mode> 0—µs
1 MHz mode(1)> 0µs
IS40Taa:sclOutput Valid from Clock100 kHz mode03540ns
400 kHz mode0900ns
1 MHz mode(1)0400ns
IS45Tbf:sdaBus Free Time100 kHz mode4.7—µsTime the bus must be free before a new transmission can start
400 kHz mode1.3—µs
1 MHz mode(1)0.5—µs
IS50CBBus Capacitive Loading—400pF
IS51TPGDPulse Gobbler Delay(2)65390ns
Note:
  1. Maximum Pin Capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
  2. Typical value for this parameter is 130 ns.
  3. These parameters are characterized but not tested in manufacturing.
Figure 40-18. UARTx Module I/O Timing Characteristics
Table 40-39. UARTx Module I/O Timing Requirements(1)

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤+85°C for Industrial

Operating temperature -40°C ≤ TA ≤ +125°C

Param

No.

SymbolCharacteristicMin.Typ.Max.UnitsConditions
UA10TBAUDUARTx Baud Time20——ns
UA11FBAUDUARTx Baud Frequency——20Mbps

BRGS = 0,CLKMOD = 0 (16x divide) or

CLKMOD = 1 (fractional)

——50MbpsBRGS = 1,CLKMOD = 0 (4x divide)
UA20TSBPMStart Bit Pulse Width to Trigger UARTx Wake-up50——ns
Note:
  1. Parameters characterized but not tested in manufacturing.
Table 40-40. ADC Module Specifications

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial 


-40°C ≤ TA ≤ +125°C for Extended

Param No.SymbolCharacteristicsMin.TypicalMax.UnitsConditions
Analog Input
AD12VINH – VINLFull-Scale Input SpanAVSS—AVDDV
AD14VINAbsolute Input VoltageAVSS – 0.3—AVDD + 0.3V
AD17RINRecommended Impedance of Analog Voltage Source(1)—100—ΩFor minimum sampling time
AD60CHOLDHold Capacitor Capacitance(2)—1—pF
AD61CPINPin Capacitance(2)—4—pFShared core
AD62RICInput resistance(2)—1000—ΩIncludes RSS
AD66VBGInternal Voltage Reference Source0.7840.80.816VFrom 3/4 band gap buffer
AD67VREFInternal 15/16 VDD Reference(2)-15515LSb
AD68TREF Internal 15/16 VDDReference Sampling Time(2)32——ns
ADC Accuracy
AD20NRResolution12 data bitsbits
AD21INL

Integral Nonlinearity

-3—3LSbVDD = 3.3V, AVDD = 3.3V

Gain error uncompensated

AD22DNL

Differential Nonlinearity

-1—2LSb
AD23GERR

Gain Error

-130—50LSb
AD24OERR

Offset Error

—5—LSb
AD23aGERR

Gain Error(2)

-15—5LSbVDD = 3.3V, AVDD = 3.3V

Gain error compensated

AD25—Monotonicity————Guaranteed
Dynamic Performance
AD34ENOBEffective Number of Bits(2,3)—10.5—bits
AD50TADADC Clock Period12.5—125nsTAD = FIN/4
AD51FTPThroughput Rate(1,4)——40Msps
Note:
  1. Parameters not characterized or tested in manufacturing.
  2. Parameters characterized but not tested in manufacturing.
  3. Characterized with a 1 kHz sine wave.
  4. Throughput includes 1.5 TAD conversion time.
  5. Data in the “Typ” column are at 3.3V, +25°C. Parameters are for design guidance only and are not tested.
Table 40-41. Die Temperature Diode Specifications(1)

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial 


-40°C ≤ TA ≤ +125°C for Extended

Param
No.SymbolCharacteristicMin.Typ.Max.UnitsComments
TD01TCOEFFTemperature Coefficient(1)—1.5—mV/C
TD02TSAMPLESampling Time0.3125——µS
Note:
  1. Parameters are for design guidance only and are not tested.
Table 40-42. High-Speed Analog Comparator Module Specifications

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial 


-40°C ≤ TA ≤ +125°C for Extended

Param
 No.SymbolCharacteristicMin.Typ.Max.UnitsComments
CM10VIOFFInput Offset Voltage-35—+35mVAll packages except 28 SSOP
-70—+70mVFor 28 SSOP package only
CM11VICMInput Common-Mode 
Voltage Range(1)AVSS—AVDDV
CM13CMRRCommon-Mode Rejection Ratio(1)60——dB
CM14TRESPLarge Signal Response(1)—5—nsV+ input step of 100 mV while 
V- input is held at AVDD/2
CM15VHYSTInput Hysteresis(1)153045mVDepends on HYSSEL[1:0]
Note:
  1. Parameters are characterized but not tested in manufacturing.
Table 40-43. DACx Module Specifications

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial 


-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymbolCharacteristicMin.Typ.Max.UnitsComments
DA02CVRESResolution12bits
DA03INLIntegral Nonlinearity Error(2)-25—35LSb
DA04DNLDifferential Nonlinearity Error(2)-5—5LSb
DA05EOFFOffset Error(2)-10—20LSbInternal node at comparator input
DA06EGGain Error(2)-10—50LSbInternal node at comparator input
DA07TSETSettling Time(1)6007502000nsOutput with 1% of desired output voltage with a 
5-95% or 95-5% step
DA08VOUTVoltage Output Range0.165—3.135VVDD = 3.3V
DA09TTRTransition Time(1)340——ns
DA10TSSSteady-State Time(1)550——ns
Note:
  1. Parameters are for design guidance only and are not tested in manufacturing.
  2. DAC output codes from 5% to 95%. DAC operational at values <5% or >95%. These parameters are characterized but not tested in manufacturing.
Table 40-44. DACx Output (DACOUTx Pins) Specifications(1)

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial 


-40°C ≤ TA ≤ +125°C for Extended

Param
No.SymbolCharacteristicMin.Typ.Max.UnitsComments
DA11RLOADResistive Output Load 
Impedance10K——Ohm
DA11aCLOADOutput Load Capacitance——30pFIncluding output pin capacitance
DA12IOUTOutput Current Drive Strength-3—3mASink and source
Note:
  1. Parameters are for design guidance only and are not tested in manufacturing.
Table 40-45. Current Bias Generator Specifications(1)

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param No.SymbolCharacteristicMin.Typ.Max.UnitsConditions
CC03I10SRC10 µA Source Current8—12µAISRCx pin
CC04ISELOUT0-200 µA Selectable Output Source Current—±15—%IBIASx pin
Note:
  1. Parameters are for design guidance only and are not tested in manufacturing.
Table 40-46. Operational Amplifier Specifications

Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

SymCharacteristicMinTypMaxUnitsComments
OA01GBWPGain Bandwidth Product(1)—50—MHzLow-Power mode
—100—MHzHigh-Power mode
OA02SRSlew Rate(1)—10—V/µsLow-Power mode.

Measured from 0.5 to 2.5 Volts with a step change in input voltage

—100—V/µsHigh-Power mode. Measured from 0.5 to 2.5 Volts with a step change in input voltage
OA03VIOFFInput Offset Voltage-3(3)-1/+1+3(3)mVUnity gain configuration, High-Power mode
OA04VIBCInput Bias Current(2)———nA
OA05VICMCommon-Mode Input Voltage Range(1)AVSS—AVDDV
OA07CMRRCommon-Mode Rejection Ratio(1)—80—dB
OA08PSRRPower Supply Rejection Ratio(1)—60—dBAt 10 kHz
OA09VOROutput Voltage Range(1)AVSS—AVDDmV0.5V input overdrive, no output loading
OA11CLOADOutput Load Capacitance(1)——30pFIncluding output pin capacitance
OA12IOUTOutput Current Drive Strength(1)—10—mASink and source
OA13PMARGINPhase Margin(1)65——degreeUnity gain
OA14GMARGINGain Margin(1)20——dBUnity gain
OA15OLGOpen-Loop Gain(1)8090—dB
Note:
  1. These parameters are not characterized or tested in manufacturing.
  2. The op amps use CMOS input circuitry with negligible input bias current. The maximum “effective bias current” is the I/O pin leakage specified by electrical Parameter DI50.
  3. Parameters are characterized but not tested in manufacturing.