32.3.1 AMPx Control Register 1
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | AMPxCON1 |
| Offset: | 0x3AB0, 0x3AB8, 0x3AC0 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| AMPEN | HPEN | UGE | DIFFCON[1:0] | OMONEN | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 15 – AMPEN Op Amp Enable/On bit
| Value | Description |
|---|---|
1 | Enables op amp module |
0 | Disables op amp module |
Bit 14 – HPEN High-Power Enable bit
| Value | Description |
|---|---|
1 | Enables Op Amp High-Power (high bandwidth) mode |
0 | Disables Op Amp High-Power mode |
Bit 13 – UGE Unity Gain Buffer Enable bit
| Value | Description |
|---|---|
1 | Enables Unity Gain mode |
0 | Disables Unity Gain mode |
Bits 12:11 – DIFFCON[1:0] Differential Input Mode Control bits
| Value | Description |
|---|---|
11 | Reserved, do not use |
10 | Turn NMOS differential input pair off |
01 | Turn PMOS differential input pair off |
00 | Use both NMOS and PMOS differential input pair |
Bit 8 – OMONEN Enable Output Monitor bit
| Value | Description |
|---|---|
1 | Enables output to ADC |
0 | Disables output to ADC |