4.6 Dedicated I/O Bank Pins

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JTAG, SPI, and DEVRST_N signals share the same bank 3 supply and are not directly available to the fabric. SPI I/O are, however, dynamically switched over to be used by the fabric whenever the RT PolarFire controller is not using them. Dedicated I/O bank supplies must be powered up above their operational threshold and enabled before the RT PolarFire controller negates the main power-on reset to the FPGA fabric. The following tables list the JTAG, SPI, and DEVRST_N pin names and descriptions. Libero configures unused user I/O as input buffer disabled, output buffer tri-stated with weak pull-up. For more information about unused conditions, see RT PolarFire FPGA Board Design User Guide.

The JTAG bank voltages can be set to operate at 1.8V, 2.5V, or 3.3V. The following table lists the JTAG pins.

Table 4-6. JTAG Pins
Pin Names	Direction	Weak Pull-Up/Unused Condition	Description
TMS	Input	Yes/DNC	JTAG test mode select
TRSTB	Input	Yes	JTAG test reset. Must be held low during device operation
TDI	Input	Yes/DNC	JTAG test data in In ATPG or test mode, when using a 4-bit tdi bus, this I/O is used as tdi[0].
TCK	Input	No	JTAG test clock
TDO	Output	No/DNC	JTAG test data out

Important: If FPGA is in System Controller Suspend Mode and TRSTB is unused, either an external 1 kΩ pull-down resistor should be connected to TRSTB to override the weak internal pull-up, or TRSTB should be driven low from the external source.

Important: In unused condition, TCK must be connected to VSS through 10 kΩ resistor.

Table 4-7. Device Reset Pins
Name	Direction	Weak Pull-up	Description
DEVRST_N	Input	22 KΩ	Device reset (asserted low).

Table 4-8. SPI Interface Pins
Name	Direction	Description
SCK	Bi-directional	SPI clock
SS	Bi-directional	SPI target select
SDI	Input	SDI input for the shared SPI interface.
SDO	Output	SDO output for the shared SPI interface.
SPI_EN	Input	Pulled up or down through a resistor or driven dynamically from an external source to enable or tri-state the SPI I/O.
IO_CFG_INTF	Input	Pulled up or down through a resistor or driven dynamically from an external source to indicate whether the shared SPI interface is an initiator or a target. Dedicated to the system controller. 0: SPI target interface 1: SPI initiator interface

Table 4-9. Special Pins
Name	Direction	Description	Unused Condition
NC	—	No connect pin. This pin indicates that it is not connected within the circuitry. NC pins can be driven by any voltage or can be left floating with no effect on the operation of the device.	—
DNC	—	Do not connect pin. DNC pins must not be connected to any signals on the PCB, and they must be left unconnected.	—
LPRB_A	Output	Specifies an internal signal for probing (oscilloscope-like feature). The two live probe I/O cells function as either of the following: Live probe User I/O (GPIO)	Libero-defined DNC
LPRB_B	Output		Libero-defined DNC
FF_EXIT_N	Input	Reserved	—
Shield Signal	Output	Shield signal is required for each DDR data byte signal. It must be driven with maximum drive strength to improve the signal integrity.	Only when DDR controller is in use