4.1 User I/O

RT PolarFire FPGA I/Os are paired up to meet the differential I/O standards and grouped into lanes of 12 buffers with a lane controller for memory interfaces. For more information about the memory controller, see PolarFire Family Memory Controller User Guide.

Two types of I/O buffers are available—HSIO and GPIO. HSIO is optimized for 1.2 Gbps (DDR4) operation with operating supplies between 1.1V and 1.8V. GPIO buffers support a wider range of I/O interfaces with speeds of up to 1066 Mbps when using single-ended standards and 1.25 Gbps when using differential standards. GPIO supports multiple standards with an integrated Clock Data Recovery (CDR) to high-speed serial interfaces such as 1 GbE.

Each RT PolarFire FPGA user I/O uses an IOxyBz naming convention, where:

• IO = the type of I/O.
• x = the I/O pair number in bank z
• y = P (positive) or N (negative). In single-ended mode, the I/O pair operates as two separate I/O—P and N. Differential mode is implemented with a fixed I/O pair and cannot be split with an adjacent I/O
• B = bank (refer note in Supported I/O Features)
• z = bank number

GPIOxyBz and HSIOxyBz are bi-directional user I/O pins that are capable of differential signaling.