4.2 Supply Pins
(Ask a Question)The following table lists multiple power supply pins required for proper device operation. For more information about unused conditions and power sequence, see RT PolarFire FPGA Board Design User Guide.
| Name | Description | Operating Voltage |
|---|---|---|
| XCVR_VREF | Voltage reference for transceiver | 0.9V/1.25V |
| VDD_XCVR_CLK | Provides common power to all transceiver reference clock buffers | 2.5V/3.3V |
| VDDA25 | Transceiver PLL power | 2.5V |
| VDDA | Power for transceiver Tx and Rx lanes 0, 1, 2, 3 | 1.0V/1.05V |
| VSS | Core digital ground | — |
| VDD | Device core digital supply | 1.0V/1.05V |
| VDDIx (JTAG Bank) | Supply for I/O circuits in a bank | 1.8V/2.5V/3.3V |
| VDDIx (GPIO Banks) | Supply for I/O circuits in a bank | 1.2V/1.5V/1.8V/2.5V/3.3V |
| VDDIx (HSIO Banks) | Supply for I/O circuits in a bank | 1.2V/1.5V/1.8V |
| VDD25 | Power for corner PLLs and PNVM | 2.5V |
| VDD18 | Power for programming and HSIO receiver. HSIO auxiliary power supply | 1.8V |
| VDDAUXx | Auxiliary supply for I/O circuits. Auxiliary supply voltage must be set to 2.5V or 3.3V and must be always equal to or higher than VDDIx of GPIO banks | Greater than or equal to VDDI |
Important: SSTL25 (stub series terminated logic) I/O standard for 1.25V VREF, SSTL18 I/O standard for 0.9V, and HSUL18 I/O standard for 0.9V.
Important: Designers should be familiar with the latest Single Event Latch-Up radiation test data before choosing GPIO supply voltages.