20.3.3 SENTx Control Register 3
| Name: | SENTxCON3 |
| Offset: | 0x88, 0xA0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SENTxCON3[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SENTxCON3[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bits 15:0 – SENTxCON3[15:0] Sync Minimum/Frame Time Control bits
Module in Receive Mode (RCVEN = 1):
SENTxCON3[15:0] value specifies the minimum time interval for a valid Sync period.
Module in Transmit Mode (RCVEN = 0):
SENTxCON3[15:0] value specifies the total number of ticks for a data frame when the pause
pulse is enabled (PPP = 1).