20.3.2 SENTx Control Register 2
| Name: | SENTxCON2 |
| Offset: | 0x84, 0x9C |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SENTxCON2[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SENTxCON2[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bits 15:0 – SENTxCON2[15:0] Sync Maximum/Tick Time Control bits
Module in Receive Mode (RCVEN = 1):
SENTxCON2[15:0] value specifies the maximum time interval for a valid Sync period.
Module in Transmit Mode (RCVEN = 0):
SENTxCON2[15:0] value specifies the period for the tick clock generator.