14.8.2 TRX_STATE
| Name: | TRX_STATE |
| Offset: | 0x02 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRAC_STATUS[2:0] | TRX_CMD[4:0] | ||||||||
| Access | R | R | R | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:5 – TRAC_STATUS[2:0] TRAC_Status
The status of the RX_AACK and TX_ARET procedure is indicated by register bits TRAC_STATUS. Values are meaningful after an interrupt until the next frame transmit. Details of the algorithm and a description of the status information are given in “RX_AACK_ON – Receive with Automatic ACK” on page 919 and “TX_ARET_ON – Transmit with Automatic Frame Retransmission and CSMA-CA Retry” on page 929.
| Value | Description | RX_AACK | TX_ARET |
|---|---|---|---|
| 0x0(1) | SUCCESS | X | X |
| 0x1 | SUCCESS_DATA_PENDING | X | |
| 0x2 | SUCCESS_WAIT_FOR_ACK | X | |
| 0x3 | CHANNEL_ACCESS_FAILURE | X | |
| 0x5 | NO_ACK | X | |
| 0x7(1) | INVALID | X | X |
| - | All other values are reserved |
- Even though the reset value for register bits TRAC_STATUS is zero, the RX_AACK and TX_ARET procedures set the register bits to TRAC_STATUS = 7 (INVALID) when they are started.
The status of the RX_AACK and TX_ARET procedures is indicated by register bits TRAC_STATUS. Values are meaningful after an interrupt until the next frame transmit. Details of the algorithms and a description of the status information are given in the RX_AACK_ON and TX_ARET_ON sections.
RX_AACK
SUCCESS_WAIT_FOR_ACK: Indicates an ACK frame is about to be sent in RX_AACK slotted acknowledgement. Slotted acknowledgement operation must be enabled with register bit SLOTTED_OPERATION (register 0x2C, XAH_XTRL_0). The microcontroller must pulse pin 11 (SLP_TR) at the next backoff slot boundary in order to initiate a transmission of the ACK frame. For details refer to IEEE 802.15.4-2006, Section 7.5.6.4.2.
TX_ARET
SUCCESS_DATA_PENDING: Indicates a successful reception of an ACK frame with frame pending bit set to one.
Bits 4:0 – TRX_CMD[4:0] TRX_CMD
A write access to register bits TRX_CMD initiate a radio transceiver state transition to the new state.
| Value | Description |
|---|---|
| 0x00(1) | NOP |
| 0x02(2) | TX_START |
| 0x03 | FORCE_TRX_OFF |
| 0x04(3) | FORCE_PLL_ON |
| 0x06 | RX_ON |
| 0x08 | TRX_OFF (CLK Mode) |
| 0x09 | PLL_ON (TX_ON) |
| 0x16(4) | RX_AACK_ON |
| 0x19(4) | TX_ARET_ON |
| Reserved | All other values are reserved |
- TRX_CMD = 0 after power on reset (POR).
- The frame transmission starts one symbol after TX_START command.
- FORCE_PLL_ON is not valid for states P_ON, SLEEP, RESET and all *_NOCLK states, as well as STATE_TRANSITION_IN_PROGRESS towards these states.
- Extended Operating Mode only.
A write access to register bits TRX_CMD initiates a radio transceiver state transition towards the new state. These register bits are used for Basic and Extended Operating Mode, see “Extended Operating Mode” on page 916