14.8.12 TRX_CTRL_2

The TRX_CTRL_2 register is a multi-purpose control register to control various settings of the radio transceiver.
Name: TRX_CTRL_2
Offset: 0x0C
Reset: 0x14
Property: -

Bit 76543210 
 RX_SAFE_MODETRX_OFF_AVDD_ENOQPSK_SCRAM_ENALT_SPECTRUMBPSK_OQPSKSUB_MODEOQPSK_DATA_RATE[1:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00100100 

Bit 7 – RX_SAFE_MODE RX_SAFE_MODE

Protect Frame Buffer after frame reception with valid FCF check.

Table 14-66. RX_SAFE_MODE
ValueDescription
0x0Disable Dynamic Frame Buffer protection
0x1(1)Enable Dynamic Frame Buffer protection
  1. Dynamic Frame Buffer Protection is released on the rising edge of pin 23 (/SEL) during a Frame Buffer read access, or on the radio transceiver’s state change from RX_ON or RX_AACK_ON to another state.

This operation mode is independent of the setting of the RX_PDT_LEVEL bits in the RX_SYN register.

Bit 6 – TRX_OFF_AVDD_EN TRX_OFF_AVDD_EN

The register bit TRX_OFF_AVDD_EN enables analog voltage regulator in TRX_OFF state.

Table 14-67. TRX_OFF_AVDD_EN
ValueDescription
0x0During TRX_OFF state analog voltage regulator is disabled.
0x1During TRX_OFF state analog voltage regulator is enabled.

If this register bit is set, the analog voltage regulator remains enabled in TRX_OFF state. This provides for a faster RX or TX turn-on time. It is especially useful when a short stopover is made in TRX_OFF state. The recharge time for capacitances is avoided in this case.

The current consumption increases by 100μA (typical).

Bit 5 – OQPSK_SCRAM_EN OQPSK_SCRAM_EN

If register bit OQPSK_SCRAM_EN is enabled, an additional chip scrambling for O-QPSK is applied for data rate 400kb/s and 1000kb/s.

Table 14-68. OQPSK_SCRAM_EN
ValueDescription
0x0Scrambler is disabled
0x1Scrambler is enabled

Bit 4 – ALT_SPECTRUM ALT_SPECTRUM

The register bit ALT_SPECTRUM controls an alternative spectrum for different modes.

Table 14-69. ALT_SPECTRUM
ValueDescription
0x0The alternative spectrum mode is disabled
0x1The alternative spectrum mode is enabled

BPSK with 40kb/s: If set to zero, a chip sequence according to IEEE 802.15.4 is used. If set to one, a modified chip sequence interoperable with IEEE 802.15.4 is used for TX and RX showing different spectrum properties (to ensure FCC 600kHz bandwidth requirement). This might be beneficial when using an external power amplifier and targeting high output power according to FCC 15.247 [5].

O-QPSK with 400kchip/s: If set to zero, pulse shaping is a combination of half-sine shaping and RC-0.2 shaping according to IEEE 802.15.4. If set to one, pulse shaping is RC-0.2 shaping. This avoids inter-chip interference which results in a significantly lower EVM, refer to Section 12.6. The peak to average ratio increases by about 1dB.

O-QPSK with 1000kchip/s: If set to zero, pulse shaping is half-sine shaping. If set to one, pulse shaping is RC-0.8 shaping. Compared with half-sine shaping, side-lobes are reduced at the expense of an increased peak to average ratio (~1dB); refer toFigure 9‑11 and Figure 9‑12, respectively. This mode is particularly suitable for the Chinese 780MHz band, refer to IEEE 802.15.4c‑2009 [3] or IEEE 802.15.4‑2011 [4].

Note:
  1. The modulation BPSK‑40 and modulation BPSK‑40‑ALT are interoperable together, with some performance degenerations.
  2. During reception, this bit is not evaluated within the AT86RF212B, so it is not explicitly required to align different transceivers with ALT_SPECTRUM in order to assure interoperability. It is very likely that this also holds for any IEEE 802.15.4‑2006 compliant O-QPSK transceiver in the 915MHz band, since the IEEE 802.15.4‑2006 requirements are fulfilled for both types of shaping.

Bit 3 – BPSK_OQPSK BPSK_OQPSK

The register bit BPSK_OQPSK controls the modulation scheme.

Table 14-70. BPSK_OQPSK
ValueDescription
0x0BPSK modulation is active
0x1O-QPSK modulation is active

Bit 2 – SUB_MODE SUB_MODE

Mode selection for European/North American/(Chinese) band.

Table 14-71. SUB_MODE
ValueDescription
0x0BPSK-20, OQPSK-{100,200,400}
0x1BPSK-40, OQPSK-{250,500,1000}

If set to one (reset value), the chip rate is 1000kchip/s for BPSK_OQPSK = 1 and 600kchip/s for BPSK_OQPSK = 0. It permits data rates out of {250, 500, 1000}kb/s or 40kb/s, respectively. This mode is particularly suitable for the 915MHz band. For O‑QPSK transmission, pulse shaping is either half-sine shaping or RC-0.8 shaping, depending on ALT_SPECTRUM.

If set to zero, the chip rate is 400kchip/s for BPSK_OQPSK = 1 and 300kchip/s for BPSK_OQPSK = 0. It permits data rates out of {100, 200, 400}kb/s or 20kb/s, respectively. This mode is particularly suitable for the 868.3MHz band. For O‑QPSK transmission, pulse shaping is always the combination of half-sine shaping and RC-0.2 shaping.

Bits 1:0 – OQPSK_DATA_RATE[1:0] OQPSK_DATA_RATE

A write access to these register bits set the O-QPSK PSDU data rate used by the radio transceiver. The reset value OQPSK_DATA_RATE = 0 is the PSDU data rate according to IEEE 802.15.4.

Table 14-72. OQPSK_DATA_RATE
ValueDescription
0x0

SUB_MODE = 0: 100kb/s or

SUB_MODE = 1: 250kb/s

0x1

SUB_MODE = 0: 200kb/s or

SUB_MODE = 1: 500kb/s

0x2

SUB_MODE = 0: 400kb/s or

SUB_MODE = 1: 1000kb/s

0x3

SUB_MODE = 0: Reserved or

SUB_MODE = 1: 500kb/s

The AT86RF212B supports two different modes with an PSDU data rate of 500kb/s. Using OQPSK_DATA_RATE = 3 might be beneficial when using an external power amplifier and targeting high output power according to FCC 15.247 [5].

In the table below all PHY modes supported by the AT86RF212B are summarized with the relevant setting for each bit of register TRX_CTRL_2. The “-“ (minus) character means that the bit entry is not relevant for the particular PHY mode.

TRX_CTRL_2 Register Bits
PHY Mode76543210Compliance
BPSK-20---00000IEEE 802.15.4‑2003/2006/2011:
channel page 0, channel 0
BPSK-40---00100IEEE 802.15.4‑2003/2006/2011:
channel page 0, channel 1 to 10
BPSK-40-ALT---10100Proprietary,
alternative spreading code
OQPSK-SIN-RC-100---01000IEEE 802.15.4‑2006/2011:
channel page 2, channel 0
OQPSK-SIN-RC-200---01001Proprietary
OQPSK-SIN-RC-400-SCR-ON--101010Proprietary, scrambler on
OQPSK-SIN-RC-400-SCR-OFF--001010Proprietary, scrambler off
OQPSK-RC-100---11000Proprietary
OQPSK-RC-200---11001Proprietary
OQPSK-RC-400-SCR-ON--111010Proprietary, scrambler on
OQPSK-RC-400-SCR-OFF--011010Proprietary, scrambler off
OQPSK-SIN-250---01100IEEE 802.15.4‑2006/2011:
channel page 2, channel 1 to 10
OQPSK-SIN-500---01101Proprietary
OQPSK-SIN-500-ALT---01111Proprietary,
alternative spreading code
OQPSK-SIN-1000-SCR-ON--101110Proprietary, scrambler on
OQPSK-SIN-1000-SCR-OFF--001110Proprietary, scrambler off
OQPSK-RC-250---11100IEEE 802.15.4‑2011:
channel page 5, channel 0 to 3
OQPSK-RC-500---11101Proprietary
OQPSK-RC-500-ALT---11111Proprietary,
alternative spreading code
OQPSK-RC-1000-SCR-ON--111110Proprietary, scrambler on
OQPSK-RC-1000-SCR-OFF--011110Proprietary, scrambler off