20.7.4 Interrupt Flag Status and Clear
| Name: | INTFLAG |
| Offset: | 0x0C |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DFLLRCS | DFLLLCKC | DFLLLCKF | DFLLOOB | DFLLRDY | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DPLLLDRTO | DPLLLTO | DPLLLCKF | DPLLLCKR | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DFLLULPNOLOCK | DFLLULPLOCK | DFLLULPRDY | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OSC16MRDY | XOSCFAIL | XOSCRDY | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 28 – DFLLRCS DFLL Reference Clock Stopped
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DFLL Reference Clock Stopped bit in the Status register (STATUS.DFLLRCS) and will generate an interrupt request if INTENSET.DFLLRCS is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DFLL Reference Clock Stopped interrupt flag.
Bit 27 – DFLLLCKC DFLL Lock Coarse
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DFLL Lock Coarse bit in the Status register (STATUS.DFLLLCKC) and will generate an interrupt request if INTENSET.DFLLLCKC is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DFLL Lock Coarse interrupt flag.
Bit 26 – DFLLLCKF DFLL Lock Fine
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DFLL Lock Fine bit in the Status register (STATUS.DFLLLCKF) and will generate an interrupt request if INTENSET.DFLLLCKF is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DFLL Lock Fine interrupt flag.
Bit 25 – DFLLOOB DFLL Out Of Bounds
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DFLL Out Of Bounds bit in the Status register (STATUS.DFLLOOB) and will generate an interrupt request if INTENSET.DFLLOOB is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DFLL Out Of Bounds interrupt flag.
Bit 24 – DFLLRDY DFLL Ready
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DFLL Ready bit in the Status register (STATUS.DFLLRDY) and will generate an interrupt request if INTENSET.DFLLRDY is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DFLL Ready interrupt flag.
Bit 19 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete
This flag is cleared by writing '1' to it.
This flag is set on a high to low transition of the DPLL Loop Divider Ratio Update Complete bit in the Status register (STATUS.DPLLLDRTO) and will generate an interrupt request if INTENSET.DPLLLDRTO is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DPLL Loop Divider Ratio Update Complete interrupt flag.
Bit 18 – DPLLLTO DPLL Lock Timeout
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DPLL Lock Timeout bit in the Status register (STATUS.DPLLLTO) and will generate an interrupt request if INTENSET.DPLLLTO is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DPLL Lock Timeout interrupt flag.
Bit 17 – DPLLLCKF DPLL Lock Fall
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DPLL Lock Fall bit in the Status register (STATUS.DPLLLCKF) and will generate an interrupt request if INTENSET.DPLLLCKF is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DPLL Lock Fall interrupt flag.
Bit 16 – DPLLLCKR DPLL Lock Rise
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DPLL Lock Rise bit in the Status register (STATUS.DPLLLCKR) and will generate an interrupt request if INTENSET.DPLLLCKR is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DPLL Lock Rise interrupt flag.
Bit 10 – DFLLULPNOLOCK DFLLULP No Lock
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DFLLULP No Lock bit in the Status register (STATUS.DFLLULPNOLOCK) and will generate an interrupt request if INTENSET.DFLLULPNOLOCK is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DFLLULP No Lock interrupt flag.
Bit 9 – DFLLULPLOCK DFLLULP Lock
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DFLLULP Lock bit in the Status register (STATUS.DFLLULPLOCK) and will generate an interrupt request if INTENSET.DFLLULPLOCK is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DFLLULP Lock interrupt flag.
Bit 8 – DFLLULPRDY DFLLULP Ready
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the DFLLULP Ready bit in the Status register (STATUS.DFLLULPREADY) and will generate an interrupt request if INTENSET.DFLLULPREADY is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the DFLLULP Ready interrupt flag.
Bit 4 – OSC16MRDY OSC16M Ready
This flag is cleared by writing '1' to it.
This flag is set on 0-to-1 transition of the OSC16M Ready bit in the Status register (STATUS.OSC16MRDY) and will generate an interrupt request if INTENSET.OSC16MRDY is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the OSC16M Ready interrupt flag.
Bit 1 – XOSCFAIL XOSC Clock Failure
This flag is cleared by writing '1' to it.
This flag is set on a 0-to-1 transition of the XOSC Clock Failure bit in the Status register (STATUS.XOSCFAIL) and will generate an interrupt request if INTENSET.XOSCFAIL is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the XOSC Clock Failure interrupt flag.
Bit 0 – XOSCRDY XOSC Ready
This flag is cleared by writing '1' to it.
This flag is set on a 0-to-1 transition of the XOSC Ready bit in the Status register (STATUS.XOSCRDY) and will generate an interrupt request if INTENSET.XOSCRDY is '1'.
Writing '0' to this bit has no effect.
Writing '1' to this bit clears the XOSC Ready interrupt flag.