20.7.16 DFLL48M Value

Note: This register is read-synchronized: prior to any read access, this register must be synchronized by user by writing the according value to the DFLLSYNC register (DFLLSYNC.READREQ=1).

Note: This register is write-synchronized: STATUS.DFLLRDY must be checked to ensure the DFLLVAL register synchronization is complete.

Name:	DFLLVAL
Offset:	0x34
Reset:	0x00000000
Property:	PAC Write-Protection, Write-Synchronized, Read-Synchronized


Bit	31	30	29	28	27	26	25	24
	DIFF[15:8]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DIFF[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	COARSE[5:0]						FINE[9:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	FINE[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:16 – DIFF[15:0] Multiplication Ratio Difference

In closed-loop mode (DFLLCTRL.MODE=1), this bit group indicates the difference between the ideal number of DFLL cycles and the counted number of cycles. In open-loop mode, this value is not updated and hence, invalid.

Bits 15:10 – COARSE[5:0] Coarse Value

Set the value of the Coarse Calibration register. In closed-loop mode, this field is read-only.

Using the "DFLL48M COARSE" value from the Non Volatile Memory Software Calibration Area helps to output a frequency close to 48MHz.

Bits 9:0 – FINE[9:0] Fine Value

Set the value of the Fine Calibration register. In closed-loop mode, this field is read-only.