20.7 Register Summary
Refer to the Registers Description section for more details on register properties and access permissions.
Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|
0x00 | EVCTRL | 7:0 | TUNEINV | TUNEEI | CFDEO | |||||
0x01 ... 0x03 | Reserved | |||||||||
0x04 | INTENCLR | 31:24 | DFLLRCS | DFLLLCKC | DFLLLCKF | DFLLOOB | DFLLRDY | |||
23:16 | DPLLLDRTO | DPLLLTO | DPLLLCKF | DPLLLCKR | ||||||
15:8 | DFLLULPNOLOCK | DFLLULPLOCK | DFLLULPRDY | |||||||
7:0 | OSC16MRDY | XOSCFAIL | XOSCRDY | |||||||
0x08 | INTENSET | 31:24 | DFLLRCS | DFLLLCKC | DFLLLCKF | DFLLOOB | DFLLRDY | |||
23:16 | DPLLLDRTO | DPLLLTO | DPLLLCKF | DPLLLCKR | ||||||
15:8 | DFLLULPNOLOCK | DFLLULPLOCK | DFLLULPRDY | |||||||
7:0 | OSC16MRDY | XOSCFAIL | XOSCRDY | |||||||
0x0C | INTFLAG | 31:24 | DFLLRCS | DFLLLCKC | DFLLLCKF | DFLLOOB | DFLLRDY | |||
23:16 | DPLLLDRTO | DPLLLTO | DPLLLCKF | DPLLLCKR | ||||||
15:8 | DFLLULPNOLOCK | DFLLULPLOCK | DFLLULPRDY | |||||||
7:0 | OSC16MRDY | XOSCFAIL | XOSCRDY | |||||||
0x10 | STATUS | 31:24 | DFLLRCS | DFLLLCKC | DFLLLCKF | DFLLOOB | DFLLRDY | |||
23:16 | DPLLLDRTO | DPLLLTO | DPLLLCKF | DPLLLCKR | ||||||
15:8 | DFLLULPNOLOCK | DFLLULPLOCK | DFLLULPRDY | |||||||
7:0 | OSC16MRDY | XOSCCKSW | XOSCFAIL | XOSCRDY | ||||||
0x14 | XOSCCTRL | 15:8 | STARTUP[3:0] | AMPGC | GAIN[2:0] | |||||
7:0 | ONDEMAND | RUNSTDBY | SWBEN | CFDEN | XTALEN | ENABLE | ||||
0x16 | CFDPRESC | 7:0 | CFDPRESC[2:0] | |||||||
0x17 | Reserved | |||||||||
0x18 | OSC16MCTRL | 7:0 | ONDEMAND | RUNSTDBY | FSEL[1:0] | ENABLE | ||||
0x19 ... 0x1B | Reserved | |||||||||
0x1C | DFLLULPCTRL | 15:8 | DIV[2:0] | |||||||
7:0 | ONDEMAND | RUNSTDBY | DITHER | SAFE | BINSE | Reserved | ENABLE | |||
0x1E | DFLLULPDITHER | 7:0 | PER[2:0] | STEP[2:0] | ||||||
0x1F | DFLLULPRREQ | 7:0 | RREQ | |||||||
0x20 | DFLLULPDLY | 31:24 | ||||||||
23:16 | ||||||||||
15:8 | ||||||||||
7:0 | DELAY[7:0] | |||||||||
0x24 | DFLLULPRATIO | 31:24 | ||||||||
23:16 | ||||||||||
15:8 | RATIO[10:8] | |||||||||
7:0 | RATIO[7:0] | |||||||||
0x28 | DFLLULPSYNCBUSY | 31:24 | ||||||||
23:16 | ||||||||||
15:8 | ||||||||||
7:0 | DELAY | Reserved | ENABLE | |||||||
0x2C ... 0x2F | Reserved | |||||||||
0x30 | DFLLCTRL | 15:8 | WAITLOCK | BPLCKC | QLDIS | CCDIS | ||||
7:0 | ONDEMAND | RUNSTDBY | USBCRM | LLAW | STABLE | MODE | ENABLE | |||
0x32 ... 0x33 | Reserved | |||||||||
0x34 | DFLLVAL | 31:24 | DIFF[15:8] | |||||||
23:16 | DIFF[7:0] | |||||||||
15:8 | COARSE[5:0] | FINE[9:8] | ||||||||
7:0 | FINE[7:0] | |||||||||
0x38 | DFLLMUL | 31:24 | CSTEP[5:0] | FSTEP[9:8] | ||||||
23:16 | FSTEP[7:0] | |||||||||
15:8 | MUL[15:8] | |||||||||
7:0 | MUL[7:0] | |||||||||
0x3C | DFLLSYNC | 7:0 | READREQ | |||||||
0x3D ... 0x3F | Reserved | |||||||||
0x40 | DPLLCTRLA | 7:0 | ONDEMAND | RUNSTDBY | ENABLE | |||||
0x41 ... 0x43 | Reserved | |||||||||
0x44 | DPLLRATIO | 31:24 | ||||||||
23:16 | LDRFRAC[3:0] | |||||||||
15:8 | LDR[11:8] | |||||||||
7:0 | LDR[7:0] | |||||||||
0x48 | DPLLCTRLB | 31:24 | DIV[10:8] | |||||||
23:16 | DIV[7:0] | |||||||||
15:8 | LBYPASS | LTIME[2:0] | ||||||||
7:0 | REFCLK[1:0] | WUF | LPEN | FILTER[1:0] | ||||||
0x4C | DPLLPRESC | 7:0 | PRESC[1:0] | |||||||
0x4D ... 0x4F | Reserved | |||||||||
0x50 | DPLLSYNCBUSY | 7:0 | DPLLPRESC | DPLLRATIO | ENABLE | |||||
0x51 ... 0x53 | Reserved | |||||||||
0x54 | DPLLSTATUS | 7:0 | CLKRDY | LOCK |