3.6.7 MPDDRC Low-Power Register


Bit	31	30	29	28	27	26	25	24
						DISTOEN_DONE	SELF_DONE	CHG_FRQ
Access						R	R	R/W
Reset						0	0	0


Bit	23	22	21	20	19	18	17	16
			UPD_MR[1:0]				ASR	APDE
Access			R/W	R/W			R/W	R/W
Reset			0	0			0	1


Bit	15	14	13	12	11	10	9	8
	SRT	SELFAUTO	TIMEOUT[1:0]
Access	R/W	R/W	R/W	R/W
Reset	0	0	0	0


Bit	7	6	5	4	3	2	1	0
						CLK_FR	LPCB[1:0]
Access						R/W	R/W	R/W
Reset						0	0	0

Bit 26 – DISTOEN_DONE DLL Disabled to DLL Enabled is Done

Indicates that the DLL Off (disabled) to DLL On (enabled) switching procedure is completed.

Bit 25 – SELF_DONE Self-Refresh is Done

Indicates that external device is in Self-refresh mode.

Bit 24 – CHG_FRQ Change Clock Frequency During Self-Refresh Mode

This mode is used to change the DDR2-SDRAM or DDR3-SDRAM input clock frequency. This mode is unique to the DDR2-SDRAM and DDR3-SDRAM devices.

Bits 21:20 – UPD_MR[1:0] Update Load Mode Register and Extended Mode Register

Used to enable or disable automatic update of the Load Mode register and Extended Mode register. This update depends on the MPDDRC integration in a system. The MPDDRC can either share or not an external bus with another controller.

Value	Name	Description
0	NO_UPDATE	Update of Load Mode and Extended Mode registers is disabled.
1	UPDATE_SHAREDBUS	The MPDDRC shares an external bus. Automatic update is done during a refresh command and a pending read or write access in the SDRAM device.
2	UPDATE_NOSHAREDBUS	The MPDDRC does not share an external bus. Automatic update is done before entering Self-refresh mode.
3	–	Reserved

Bit 17 – ASR Auto Self-Refresh

This mode is unique to DDR3-SDRAM devices supporting an extended temperature range. In this mode, SRT must be disabled.

Value	Description
0	DRAM manages Self-refresh entry in either the normal or extended temperature range. In this mode, DRAM manages Self-refresh power consumption when operating conditions change - lower at low temperatures and higher at high temperatures.
1	Manual Self-refresh reference must be applied.

Bit 16 – APDE Active Power Down Exit Time

This mode is unique to the DDR2-SDRAM and DDR3-SDRAM devices.

This mode manages the active Power-down mode which determines performance versus power saving.

After the initialization sequence, as soon as the APDE field is modified, the Extended Mode register (located in the memory of the external device) is accessed automatically and APDE bits are updated. Depending on the UPD_MR bit, update is done before entering Self-refresh mode or during a refresh command and a pending read or write access

Value	Name	Description
0	DDR2_FAST_EXIT	Fast exit from power-down. DDR2-SDRAM and DDR3-SDRAM devices only.
1	DDR2_SLOW_EXIT	Slow exit from power-down. DDR2-SDRAM and DDR3-SDRAM devices only.

Bit 15 – SRT High Temperature Self-Refresh Rate

This mode is unique to DDR2-SDRAM and DDR3-SDRAM devices supporting the extended temperature range.

Value	Description
1	2x refresh rate. Provides a faster rate on industrial and automotive devices if temperature exceeds 85°C.
0	1x refresh rate. Industrial and automotive devices with temperatures that do not exceed 85°C.

Bit 14 – SELFAUTO Self-Refresh Exit Auto-Refresh

Value	Description
1	Upon exiting Self-refresh mode, auto-refresh command is immediately performed after t_XSNR.
0	Upon exiting Self-refresh mode, active command is immediately performed after t_XSNR. The auto-refresh command is issued every 15.6 µs or less.

Bits 13:12 – TIMEOUT[1:0] Time Between Last Transfer and Low-Power Mode

Defines when Low-power mode is activated.

Value	Name	Description
0	NONE	SDRAM Low-power mode is activated immediately after the end of the last transfer.
1	DELAY_64_CLK	SDRAM Low-power mode is activated 64 clock cycles after the end of the last transfer.
2	DELAY_128_CLK	SDRAM Low-power mode is activated 128 clock cycles after the end of the last transfer.
3	–	Reserved

Bit 2 – CLK_FR Clock Frozen Command Bit

Sets the clock low during Power-down mode. Some DDR-SDRAM devices do not support freezing the clock during Power-down mode. Refer to the relevant DDR-SDRAM device data sheet for details.

Value	Name	Description
0	DISABLED	Clock(s) is/are not frozen.
1	ENABLED	Clock(s) is/are frozen.

Bits 1:0 – LPCB[1:0] Low-power Command Bit

Value	Name	Description
0	NOLOWPOWER	Low-power feature is inhibited. No Power-down, Self-refresh and Deep power modes are issued to the DDR-SDRAM device.
1	SELFREFRESH	The MPDDRC issues a self-refresh command to the DDR-SDRAM device, the clock(s) is/are deactivated and the CKE signal is set low. The DDR-SDRAM device leaves the Self-refresh mode when accessed and reenters it after the access.
2	POWERDOWN	The MPDDRC issues a Power-down command to the DDR-SDRAM device after each access, the CKE signal is set low. The DDR-SDRAM device leaves the Power-down mode when accessed and reenters it after the access.

Name:	MPDDRC_LPR
Offset:	0x1C
Reset:	0x00010000
Property:	Read/Write