| Changed datasheet status from ‘Preliminary’ to
‘Complete’. |
| Added “Introduction” and transferred Description to
Section 1. |
| Section 2. “Configuration Summary” |
| Added device compatibility information |
| Section 4. “Signal Description” |
| Table 4-1 “Signal Description List”: modified rows PIOBU
0-7 and DDR_RESETN |
| Section 6. “Power Considerations” |
| Added Section 6.4.1 “VDDBU Power Architecture” |
| Updated Section 6.2 “Power-Up Considerations” and Section
6.3 “Power-Down Considerations” |
| Section 7. “Memories” |
| Updated Section 7.1.2 “Internal ROM” |
| Section 10. “Peripherals” |
| Updated Table 10-1 “Peripheral identifiers” and Section
10.4 “Peripheral Clock Types” |
| Section 16. “AXI Matrix (AXIMX)” |
| Table 16-1 “Register Mapping”: removed 0x00000000 reset
value from all rows |
| Section 17. “Matrix (H64MX/H32MX)” |
| Section 17.2 “Embedded Characteristics”: removed "Master
number forwarding to slaves" characteristic |
| Updated Table 17-1 “List of H64MX Masters”, Table 17-2
“List of H64MX Slaves”, Table 17-4 “List of H32MX Masters”, Table 17-5
“List of H32MX Slaves” |
| Table 17-3 “Master to Slave Access on H64MX”: updated
‘SDMMC0-SDMMC1’ row |
| Table 17-6 “Master to Slave Access on H32MX”: updated
‘Slave 5’ rows |
| Section 17.12.2 “Security of APB Slaves”: added
introduction and bulleted list introduced by “As a general rule” |
| Added Section 17.12.3 “Security Types of AHB Master
Peripherals” and Section 17.12.4 “Security Types of AHB Slave
Peripherals” |
| Section 17-9 “Peripheral Identifiers”: corrected some
security type names |
| Section 17.13 “AHB Matrix (MATRIX) User Interface”:
added introduction and modified reset value of Updated Security Areas
Split Slave x Registers in Table 17-10 “Register Mapping” |
| Section 21. “Watchdog Timer (WDT)” |
| Replaced “Idle mode” with “Sleep mode (Idle mode)” in
Section 21.1 “Description” and with “Sleep mode” in Section 21.4
“Functional Description” |
| Section 22. “Reset Controller (RSTC)” |
| Renamed 'proc_nreset' to 'Processor Reset',
'periph_nreset' to 'Peripheral Reset', 'backup_neset' to 'Backup Reset',
'rstc_irq' to 'Reset Controller Interrupt', 'wd_fault' to 'Watchdog
Fault', ‘user_reset’ to User Reset. |
| Updated text and figures to show that Processor Reset
and Peripheral Reset signals are merged. |
| Section 23. “Shutdown Controller (SHDWC)” |
| Updated Figure 23-1 “Shutdown Controller Block Diagram”
and Table 23-1 “I/O Lines Description” |
| Section 23.7.3 “Shutdown Status Register”: corrected
register table (added WKUPIS9) |
| Section 23.7.4 “Shutdown Wake-up Inputs Register”:
corrected register table (added WKUPT9 and WKUPEN9) |
| Section 25. “Real-time Clock (RTC)” |
| Removed RTC Milliseconds Register (RTC_MSR) and all
related information in Section 25.1 “Description”, Section 25.2
“Embedded Characteristics”, Section 25.5 “Functional Description” and
Section 25.6 “Real-time Clock (RTC) User Interface”. |
| Table 25-1 “Register Mapping”: modified RTC_CALR reset
value |
| Section 25.6.1 “RTC Control Register”: updated CALEVSEL
field description |
| Updated Section 25.6.22 “RTC TimeStamp Source
Register” |
| Section 29. “Clock Generator” |
| Section 29.2 “Embedded Characteristics”: replaced "400
to 1000 MHz programmable PLL" with "600 to 1200 MHz programmable PLL"
and replaced “HCLOCK” with “HCLOCK_LS/HS” and “PCLOCK” with
“PCLOCK_LS/HS” |
| Section 29.4 “Slow Clock”: removed “This allows the slow
clock to be valid in a short time (about 100 μs)” |
| Section 29.8 “Audio PLL”: updated all equations and
added “in the 700 MHz range” after “The PLL core operates at 700 MHz
(AUDIOCORECLOCK)” |
| Updated Figure 29-3. Main Clock Block Diagram and Figure
29-4. Main Clock Source Selection |
| Section 30. “Power Management Controller
(PMC)” |
| Updated Section 30.6 “Matrix Clock Controller” |
| Updated Section 30-1 “General Clock Block
Diagram” |
| Section 30.19 “Programming Sequence”, sub-section
“Selecting Master Clock and Processor Clock”: updated sequence following
"If a new value for CSS field corresponds to PLL Clock" |
| Section 30.22.11 “PMC Master Clock Register”: updated
H32MXDIV field description |
| Section 33. “Multi-port DDR-SDRAM Controller
(MPDDRC)” |
| Section 33-2 “Single Write Access, Row Closed, DDR-SDRAM
Devices” to Section 33-8 “SINGLE Write Access Followed by a Read Access,
DDR2-SDRAM Devices”: replaced “D[15:0]” with “DATA” |
| Updated Section 33.7.9 “MPDDRC Low-power DDR2 Low-power
DDR3 Low-power Register” |
| Section 33.7.10 “MPDDRC Low-power DDR2 Low-power DDR3 and
DDR3 Calibration and MR4 Register”: updated MR4_READ field
description |
| Section 34. “Static Memory Controller
(SMC)” |
| Removed NFCCMD field and modified Section 34.17.2.1
“Building NFC Address Command Example” and Section 34.17.2.2 “NFC
Address Command” accordingly |
| Table 34-20 “Register Mapping”: corrected offset values
of PMECC Error Location 31 Register and of subsequent reserved range;
removed reset value from HSMC_CTRL (register is write-only) |
| Section 35. “DMA Controller (XDMAC)” |
| Section 35.5.4.1 “Single Block With Single Microblock
Transfer”: added text on memory-to-memory transfer |
| Section 35.8 “XDMAC Software Requirements”: added bullet
on memory-to-memory transfer |
| Table 35-5 “Register Mapping”: corrected access of
XDMAC_GTYPE, XDMAC_GWAC, XDMAC_CIM |
| Section 35.9.6 “XDMAC Global Interrupt Mask Register”:
corrected access to Read-only |
| Section 35.9.28 “XDMAC Channel x [x = 0..15]
Configuration Register”: corrected INITD and PERID field
descriptions |
| Section 36. “LCD Controller (LCDC)” |
| Modified width of fields in Section 36.7.2 “LCD
Controller Configuration Register 1” and Section 36.7.3 “LCD Controller
Configuration Register 2” |
| Section 40. “Audio Class D Amplifier
(CLASSD)” |
| Replaced ‘audio clock’ with ‘generic clock’ and ‘ACLK’
with ‘GCLK’ throughout the section |
| Section 41. “Inter-IC Sound Controller
(I2SC)” |
| Section 41.6.3 “Master, Controller and Slave Modes”:
removed text fragment: ‘in order to avoid unwanted glitches on the I2SWS
and I2SCK pins.’ |
| Section 41.8.2 “Inter-IC Sound Controller Mode
Register”: removed text fragment: ‘in order to avoid unexpected behavior
on the I2SWS, I2SCK and I2SDO outputs.’ and added note (2) below IMCKDIV
field description. |
| Section 44. “Flexible Serial Communication Controller
(FLEXCOM)” |
| Restored all references to ISO7816 specification |
| Updated Figure 44-3 “Fractional Baud Rate
Generator” |
| Added Figure 44-27 “RTS line software control when
FLEX_US_MR.USART_MODE = 2” |
| Section 44.10.6 “USART Mode Register”: updated
USART_MODE field description (SPI_MASTER item) |
| Section 44.10.44 “SPI Mode Register”: added LBHPC
bit |
| Section 45. “Universal Asynchronous Receiver
Transmitter (UART)” |
| Section 45.6.9 “UART Baud Rate Generator Register”: in
CD field description, corrected equation after “If BRSRCCK = 1” |
| Section 47. “Quad SPI Interface (QSPI)” |
| Section 47.7.5 “QSPI Status Register”: updated RDRF,
TDRE, TXEMPTY, and OVRES field descriptions |
| Section 48. “Secure Digital Multimedia Card
(SDMMC)” |
| Section 48.12.41 “SDMMC Preset Value Register”: updated
CLKGSEL field description |
| Section 49. “Image Sensor Controller
(ISC)” |
| Section 49.1 “Description”: removed "serial csi-2 based
CMOS/CCD sensor" (not supported). |
| Section 50. “Controller Area Network
(MCAN)” |
| Changed MCAN interrupt line names to MCAN_INT0 and
MCAN_INT1 thoughout the section |
| Section 50.6.7 “MCAN CC Control Register”: added bit
NISO |
| Section 51. “Timer Counter (TC)” |
| Reformatted and renamed Table 51-2 “Channel Signal
Description” |
| Section 51.6.3 “Clock Selection”: updated notes (1) and
(2) |
| Section 52. “Pulse Density Modulation Interface
Controller (PDMIC)” |
| Replaced all instances of “PCK” with “GCLK” |
| Section 52.2 “Embedded Characteristics”: removed
‘Multiplexed PDM Input Support’ characteristic |
| Updated Section 52.5.2 “Power Management” and Section
52.6.2.1 “Description” |
| Section 52.6.2.6 “Gain and Offset Compensation”: updated
dgain bullet |
| Section 52.7.3 “PDMIC Converted Data Register”: updated
DATA field description |
| Section 52.7.8 “PDMIC DSP Configuration Register 0”:
updated OSR field description |
| Section 61. “Security Module” |
| Section 61.5.5 “SECUMOD Status Clear Register”: removed
MCKM field description |
| Section 61.5.18 “SECUMOD Wake Up Register”: removed TPML
field description |
| Section 62. “Analog-to-Digital Converter
(ADC)” |
| Section 62.7.2 “ADC Mode Register”: updated TRACKTIM and
TRANSFER field descriptions. |
| Section 63. “Electrical Characteristics” |
| Updated tables from Table 63-2 “DC Characteristics” to
Table 63-33 “Analog Comparator Characteristics” |
| Updated Figure 63-2 “Main Oscillator Schematics” |
| Corrected Gain Error formula under Figure 63-5 “Gain and
Offset Errors in Single-ended Mode” |
| Removed Figure 63-4 “Single-ended Mode ADC” and Figure
63-5 “Differential Mode ADC” |
| Updated wake-up pin numbers in Section 63.5.1 “Backup
Mode” and Section 63.5.3.2 “ULP1 Mode” |
| Updated Section 63.5.4 “Idle Mode” and Section 63.23
“SDMMC Timings” |
| Section 63.14.3 “Timing Extraction”: added introduction
and Figure 63-11 “MISO Capture in Master Mode” |
| Section 65. “Schematic Checklist” |
| Removed Table 65-12. “EBI Pins and NAND Flash Device
Connections” and Table 65-13. “DDR2 I/O Lines Usage vs Operating
Modes” |
| Reorganized Section 67. “Ordering
Information” |
| Updated Section 68. “Errata” |
