| Global | Editorial changes throughout. |
| System Controller | Updated Block Diagram. |
| External Memories | I/O Lines Usage vs. Operating Mode: updated unit. |
| CPU System Bus Matrix (CPUMX) |
Block Diagram: added.
Description: updated.
Embedded Characteristics: updated.
Remap: updated.
|
| Matrix (H64MX/H32MX) |
Table Host to Client Access on H32MX:
updated.
Table Peripheral Identifiers:
- updated PMC/PID1, PIT/PID3, WDT/PID4 and RSTC/PID73
- updated Note(3)
|
| Watchdog Timer (WDT) |
Block Diagram: updated.
Functional Description: updated.
WDT_CR: updated LOCKMR description.
|
| Reset Controller (RSTC) |
Block Diagram: modified.
Embedded Characteristics: updated.
32.768 kHz Crystal Oscillator Failure Detection Reset:
added.
Reset State Priorities: updated.
RSTC_SR: updated RSTTYP description.
RSTC_MR: added SCKSW at index 1, and description.
|
| Real-time Clock (RTC) |
Embedded Characteristics: updated.
Waveform Generation: updated.
RTC_CALR: updated.
Updated bit descriptions in RTC_CR, RTC_MR, RTC_TIMALR, RTC_CALALR.
|
| Slow Clock Controller (SCKC) |
Description: updated.
Block Diagram: updated.
Functional Description: updated.
|
| Clock Generator |
12 MHz RC Oscillator Clock Frequency Adjustment: deleted.
|
| Power Management Controller (PMC) |
Throughout: SLCK renamed to TD_SLCK.
Figure Main System Bus Clock Controller:
updated.
Programmable Clock Controller: updated.
Asynchronous Partial Wake-Up: updated.
Register Summary: offset 0x0110 now ‘reserved’.
|
| Parallel Input/Output Controller (PIO) |
General Purpose or Peripheral Function Selection:
updated.
Open-Drain Mode: added note.
Input Glitch and Debouncing Filters: updated.
|
| DDR-SDRAM Controller (MPDDRC) |
Product Dependencies, Initialization Sequence: added new
step in initialization sequences
MPDDRC_CR: updated DIS_DLL and NDQS descriptions.
|
| Static Memory Controller (SMC) |
Embedded Characteristics: updated NFC_RAM
characteristics.
HSMC_PMECCFG: updated SPAREEN and AUTO bit
descriptions.
|
| DMA Controller (XDMAC) |
Updated memory-to-memory transfer information in: |
| LCD Controller (LCDC) |
Embedded Characteristics: modified bullets on Output
mode.
Window Position, Size, Scaling and Striding Attributes:
table title changed to “Window Size” from “YUV Mode and Window
Size”.
YUV Frame Buffer Memory Mapping: replaced “interleaved”
with “packed” throughout.
|
| Gigabit Ethernet MAC (GMAC) |
Embedded Characteristics, Priority Queueing in the DMA: updated.
1588 Timestamp Unit: updated.
Updated table Receive Buffer Descriptor Entry.
Data Paths with Packet Buffers Included:
modified figure (GMII becomes PHY TX Interface, PHY RX
Interface)
Updated MAC Transmit Block.
Interrupts: modified first sentence.
GMAC_NCR: modified bit descriptions.
GMAC_NCFGR: modified text for DBW and IRXER.
GMAC_TSR: added text for TXGO and HRESP.
GMAC_RBQB, GMAC_TBQB: modified text.
GMAC_RXUDAR, GMAC_TXUDAR: added.
|
| USB Device High Speed Port (UDPHS) |
Block Diagram: updated.
UDPHS_CTRL: updated EN_UDPHS bit description
|
| USB Host High Speed Port (UHPHS) |
UHPHS_ASYNCLISTADDR: removed sentence referring to
non-existing UHPHS_CTRLDSSEGMENT register.
Corrected reset values for: |
| Flexible Serial Communication Controller (FLEXCOM) |
Figure 46-2 and Figure 46-3: updated
RS485 Mode: Updated figure Example of RTS Drive with Timeguard and added Note.
Local Loopback Test Mode: added
Data Transfer:
Digital Filter: added.
FLEX_TWI_FILTR: added note.
|
| Serial Peripheral Interface (SPI) |
Local Loopback Test Mode: added.
Data Transfer: updated SPI Bus Prototcol Modes and figure
titles.
|
| Quad Serial Peripheral Interface (QSPI) |
QSPI Block Diagram: modified.
Serial Clock Phase and Polarity: modified.
Table QSPI Bus Clock Modes: modified.
Scrambling/Unscrambling Function: updated.
SPI Local Loopback Test Mode: added.
QSPI_MR: modified SMRM.
QSPI_SCR: modified CPHA, CPOL.
|
| Image Sensor Controller (ISC) |
ISC Clock Management: updated.
ISC_CC_GB_OG: renamed field from ROFST to GOFST.
|
| Controller Area Network (MCAN) |
Power Management: removed “To achieve these frequencies,
PMCGCLK must select the UPLLCK (480 MHz) as source clock and divide
by 24,12, or 6.”
Standard Message ID Filter Element: corrected SFT
index.
Register Summary: offset 0x08 now ‘reserved’
|
| Timer Counter (TC) |
Embedded Characteristics: modified.
Table 53-2: modified.
Added note under Pin List
Timer Counter Clock Assignment: deleted note on
TIMER_CLOCK5.
Interrupt Sources: modified.
Clock
Selection: modified.
TC_EMR: updated TRIGSRCB description.
|
| Pulse Width Modulation Controller (PWM) |
Throughout: updated number of comparison units.
PWM Controller Block Diagram: modified.
Fault Protection: modified.
External Trigger Mode Block Diagram:
added.
Cycle-By-Cycle Duty Mode: LED String Control:
modified.
Recoverable Fault: added 1 paragraph.
PWM External Trigger Mode: modified and new content
added.
Application Example: modified.
|
| Advanced Encryption Standard Bridge (AESB) |
Interrupt Sources: modified title and content.
|
| Secure Hash Algorithm (SHA) |
Throughout: updated FIPS specification reference
Updated Internal Registers for Initial Hash Value or
Expected Hash Result
Manual Mode: modified step 4 & step 8
DMA Mode: added Note
Automatic Padding, SHA_MSR: added note
SHA_CR: updated FIRST bit description
SHA_IDATARx: updated IDATA field description
|
| True Random Number Generator (TRNG) |
Figure 62-1: updated.
|
| Analog Comparator Controller (ACC) | ACC_WPSR: updated bit descriptions. |
| Security Module (SECUMOD) |
Updated:
|
| Electrical Characteristics | Updated: Example of LSB Computation Gain and Offset Errors GMAC Timing Constraints |
| Schematic Checklist | Removed from data sheet to create standalone document, SAMA5D2
Hardware Design Considerations. |
