70.13 Revision 11267B

Changes
“Features”
Updated Security features
Section 2. “Block Diagram”
Updated Figure 2-1 “SAMA5D2 Series Block Diagram”.
Section 4. “Package and Pinout”
Updated Table 4-2 “Pin Description”
Removed Section 4.2 “Input/Output Description” and Section 4-3 “SAMA5D2 I/O Type Description”
Section 5. “Power Considerations”
Updated Table 5-1 “SAMA5D2 Power Supplies”
Updated Figure 5-1 “Recommended Power-Up Sequence”, Figure 5-2 “Recommended Power-Down Sequence”, Figure 5-3 “Recommended Backup Mode Entry”, Figure 5-4 “Recommended Power Supply Sequencing at Wake-Up”
Section 7. “Event System”
Updated Table 7-1 “Real-time Event Mapping List”
Section 14. “Standard Boot Strategies”
Replaced all instances of "GPBR" with "BUREG".
Section 17. “Special Function Registers (SFR)”
Updated Section 17.3.15 “I2S Register”
Section 19. “Advanced Interrupt Controller (AIC)”
Removed Sections “Interrupt Vectoring” and “Fast Interrupt Vectoring”
Updated Section 19.8.3.3 “Interrupt Handlers”and Section 19.8.4.3 “Fast Interrupt Handlers”
Section 29. “Power Management Controller (PMC)”
Replaced “generated clock” with “generic clock”, and “GCK” with “GCLK”
Updated Section 29.22.8 “PMC Clock Generator Main Oscillator Register”
Section 30. “Parallel Input/Output Controller (PIO)”
Removed all references to programmable I/O delay
Added Section 31. “External Memories”
Section 32. “Multi-port DDR-SDRAM Controller (MPDDRC)”
Section 32.4.3 “Low-power DDR2-SDRAM Initialization”: added Step 14., Step 15. and Step 21.
Section 32.4.5 “Low-power DDR3-SDRAM Initialization”: added Step 14., Step 15. and Step 21.
Section 32.7.8 “MPDDRC Memory Device Register”: updated DBW field description; corrected location of fields RL3 and WL
Section 36. “Ethernet MAC (GMAC)”
Updated Section 36.1 “Description”
Section 36.5.2 “Power Management”: deleted reference to PMC_PCER
Section 36.5.3 “Interrupt Sources”: deleted reference to ‘Advanced Interrupt Controller’. Replaced by ‘Interrupt Controller’.
Section 36.6.14 “IEEE 1588 Support”: deleted reference to GMAC_TSSx. Removed reference to ‘output pins’ in 2nd paragraph.
Section 36.6.15 “Time Stamp Unit”: added information on GTSUCOMP signal in last paragraph
Section 39. “Audio Class D Amplifier (CLASSD)”
Updated Figure 39-1. CLASSD Block Diagram
Section 40. “Inter-IC Sound Controller (I2SC)”
Replaced all instances of “PCKx” with “GCLK”
Removed all references to Time Division Multiplexed (TDM) format (not supported)
Section 40.1 “Description”: replaced “The I2SC can use either a single DMA Controller channel for both audio channels or one DMA Controller channel per audio channel.” with “The I2SC uses a single DMA Controller channel for both audio channels.”, and updated Section 40.2 “Embedded Characteristics” and Section 40.6.8 “DMA Controller Operation” accordingly
Section 40.8.2 “Inter-IC Sound Controller Mode Register”: removed fields RXDMA and TXDMA
Section 43. “Flexible Serial Communication Controller (FLEXCOM)”
Added SPI mode in UART/USART
Replaced all instances of ‘PCK’ with ‘GCLK’
Replaced all instances of ‘DMAC/PDC’ with ‘DMAC’
Removed SleepWalking characteristic from UART/USART mode
Removed all references to ISO7816 specification
Section 43.10.6 “USART Mode Register” updated USCLKS field description
Section 43.10.42 “SPI Mode Register”: updated BRSRCCLK and DLYBCS field descriptions
Section 43.10.52 “SPI Chip Select Register”: updated CSNAAT, SCBR, DLYBS and DLYBCT field descriptions
Section 43.10.62 “TWI Clock Waveform Generator Register”: updated BRSRCCLK and CKSRC field descriptions
Updated Figure 43-1 “FLEXCOM Block Diagram” and Figure 43-63 “Master Mode Block Diagram”
Section 42. “Two-wire Interface (TWIHS)”
Replaced all instances of “PMC_PCK” with “GCLK”
Section 44. “Universal Asynchronous Receiver Transmitter (UART)”
Replaced "Processor-Independent Source Clock" with "Processor-Independent Generic Source Clock" and "PCK" with "GCLK"
Section 47. “Secure Digital Multimedia Card (SDMMC)”
Updated revision of supported e.MMC specification (from V4.41 to V4.51)
Section 51. “Pulse Density Modulation Interface Controller (PDMIC)”
Removed all references to PDC
Removed Section 1.6.4 “Buffer Structure”
Section 53. “Secure Fuse Controller (SFC)”
Removed all references to lock fuse (not supported)
Section 53.4.5.3 “Fuse Masking”: corrected data register names
Section 53.5.2 “SFC Mode Register”: updated MSK field description
Table 53-1 “Register Mapping”: modified SFC_IER and SFC_IDR access type from “Read/Write” to “Write-only”
Section 56. “Advanced Encryption Standard (AES)”
Updated Figure 56-12 “Generation of an ESP IPSec Frame without ESN” and Figure 56-13 “Generation of an ESP IPSec Frame with ESN”
Added Section 60. “Security Module”
Section 61. “Analog-to-Digital Converter (ADC)”
Updated enhanced resolution value from 12 bits to 14 bits
Renamed “Hold time” to “Transfer time”
Replaced all instances of “PMC PCK” with “GCLK”
Added Section 61.6.6 “Conversion Results Format”, Section 61.7.13 “ADC Last Channel Trigger Mode Register”, Section 61.7.14 “ADC Last Channel Compare Window Register”
Section 61.2 “Embedded Characteristics”: corrected conversion rate
Section 61.6.9 “Comparison Window”: added paragraph about bit SIGNMODE
Section 61.6.14 “Automatic Error Correction”: replaced “GAIN_ERROR_SIZE-1” with appropriate value; replaced “Gs-1” with “Gs” in formulas
Section 61.6.14 “Automatic Error Correction”, Section 61.7.27 “Correction Values Register”: replaced “GAIN_ERROR_SIZE-1” and “OFFSET_ERROR_SIZE-1” with appropriate values
Section 61.7.2 “ADC Mode Register”: updated TRGSEL and TRACKTIM field descriptions
Updated Section 61.7.8 “ADC Last Converted Data Register”
Section 61.7.16 “ADC Extended Mode Register”: added bit SIGNMODE
Updated Section 61.7.18 “ADC Channel Offset Register”
Updated Figure 61-1 “Analog-to-Digital Converter Block Diagram” and Figure 61-7 “Analog Full Scale Ranges in Single-Ended/Differential Applications”
Updated Table 61-5 “Oversampling Digital Output Range Values”
Section 62. “Electrical Characteristics”
Added:
- Section 62.11 “Analog Comparator Characteristics”
- Section 62.14.1 “Maximum SPI Frequency”
- Section 62.16.1 “Maximum QSPI Frequency”
- Table 62-3 “I/O Switching Frequency”
- Table 62-4 “QSPI I/O Switching Frequency”
- Table 62-21 “PLL UTMI Characteristics”
- Table 62-22 “PLLAUDIO Characteristics”
Updated:
- Table 62-1 “Absolute Maximum Ratings*”
- Table 62-2 “DC Characteristics”
- Table 62-6 “Typical Peripheral Power Consumption by Peripheral in Active Mode” to Table 62-10 “Typical Power Consumption for Backup Mode”
- Table 62-13 “8 to 24 MHz Crystal Oscillator Characteristics”
- Table 62-16 “12-MHz RC Oscillator Characteristics” to Table 62-21 “PLL UTMI Characteristics”
- Table 62-34 “VDDBU Power-On Reset Characteristics” to Table 62-36 “VDDANA Power-On Reset Characteristics”
Reworked Section 62.9 “USB HS Characteristics”
Section 64. “Schematic Checklist”
Updated:
- Section 64.16.3 “DDR Layout and Design Considerations”
- Figure 64-1 “1.2V, 1.35V/1.5V, 2V, 2.5V, 3.3V Power Supplies Schematics(1)”
- Table 64-1 “Power Supply Connections”