70.11 Revision 11267D

Changes
Minor formatting and editorial changes throughout
“Introduction”
Updated listed DDR memories
“Features”
Frequency of digital fractional PLL for audio “11.289 MHz” corrected to “11.2896 MHz”
“Two 64-bit, 16-channel DMA controllers” changed to “51 DMA Channels including two 16-channel 64-bit Central DMA Controllers”
Section 1. “Description”
Updated description of Low-power modes
Section 2. “Configuration Summary”
“Class D amplifier” changed to “stereo Class D amplifier”
Updated text at end of section
Section 3. “Block Diagram”
Figure 3-1 “SAMA5D2 Series Block Diagram”: added ISC_MSK input; updated description of crystal oscillators; “PWMEXTRIG0-1” renumbered to “PWMEXTRG1–2”
Added note “See Section 35. “DMA Controller (XDMAC)” for peripheral connections to DMA.”
Section 4. “Signal Description”
Table 4-1 “Signal Description List”: NRST signal function “Microcontroller Reset” changed to “Microprocessor Reset”; “PWMEXTRG0-1” renumbered to “PWMEXTRG1–2”; “Self-refresh mode” changed to “Backup Self-refresh mode” in DDR_CKE comments
Section 5. “Package and Pinout”
Separated content into Section 5.1 “Packages” and Section 5.2 “Pinouts”
Table 5-2 “Pin Description (SAMA5D21, SAMA5D22, SAMA5D24, SAMA5D26, SAMA5D27, SAMA5D28A)”: “ADVREFP” corrected to “ADVREF”; “PWMEXTRG0” and “PWMEXTRG1” renumbered to “PWMEXTRG1” and “PWMEXTRG2”; removed empty function cells for primary signals PA30, PA31, and PB0–PB7; removed “SEC, FILTER” from “Reset State” column header; added footnote on reset states
Added Table 5-3 “Pin Description (SAMA5D23 pins different from those in SAMA5D21/SAMA5D2)” and Table 5-4 “Pin Description (SAMA5D28B pins different from those in SAMA5D28A)”
Section 6. “Power Considerations”
Table 6-1 “SAMA5D2 Power Supplies”: updated rows VDDUTMIC, VDDHSIC and VDDOSC
Section 6.4.1 “VDDBU Power Architecture”: reworded second paragraph and deleted “typically less than 2 µA”
Section 7. “Memories”
Section 7.2.1 “External Bus Interface”: “The slew rates are determined by programming the SFR_EBICFG bit in SFR registers” changed to “The drive levels are configured with the DRIVEx field in the EBI Configuration Register (SFR_EBICFG)”
Section 8. “Event System”
Section 8-1 “Real-time Event Mapping List”: instance of “ADC_ADTRG” corrected to “ADTRG”
Section 9. “System Controller”
Section 9.1 “Power-On Reset”: “dedicated to VDDBU, VDDIOP and VDDCORE” changed to “dedicated to monitoring VDDBU, VDDIOP and VDDCORE”
Section 10. “Peripherals”
Table 10-1 “Peripheral identifiers”: in ‘Instance Name’ column, renamed CAN0 and CAN1 to MCAN0 and MCAN1
Section 10.4 “Peripheral Clock Types”: in SLOW_CLOCK description, “32768-Hz crystal oscillator or by the on-chip 32-kHz RC oscillator” changed to “32.768 kHz crystal oscillator or by the on-chip 64 kHz RC oscillator”
Section 11. “Chip Identifier (CHIPID)”
Updated Table 11-1 “SAMA5D2 Chip ID Registers”
Section 13. “L2 Cache Controller (L2CC)”
Table 13-2 “Register Mapping”: reset value 0x0000_0000 changed to 0x0000_0111 for L2CC_TRCR and L2CC_DRCR
Section 14. “Debug and Test Features”
Table 14-1 “Debug and Test Pin List”: NRST pin function “Microcontroller Reset” changed to “Microprocessor Reset”
Section 15. “Standard Boot Strategies”
“Boot Sequence Control Register (BSCR)” renamed to “Boot Sequence Controller Configuration Register”
Section 15.1 “Description”: “This microcontroller can be configured” changed to “This microprocessor can be configured”
Figure 15-10 “Galois Field Table Mapping”: modified Galois field table offsets
Section 15.4.2 “Boot Sequence Controller Configuration Register”: added address
Section 15.4.3 “Boot Configuration Word”: added reference to “Customer Fuse Matrix”
Added Section 15.4.6.5 “QSPI Flash Boot”
Table 15-3 “PIO Driven during Boot Program Execution”: NAND Flash PIO line PIOC17 changed to PIOB0
Section 18. “Special Function Registers (SFR)”
Table 18-1 “Register Mapping”: removed EBI Configuration Register / SFR_EBICFG (offset 0x40 now reserved)
Section 18.3.1 “DDR Configuration Register”: added note
Removed section “EBI Configuration Register”
Section 21. “Watchdog Timer (WDT)”
Section 21.4 “Functional Description”: in eighth paragraph, “To prevent a software deadlock that continuously triggers the watchdog, the reload of the watchdog must occur...” changed to “The reload of the watchdog must occur...”
Section 25. “Real-time Clock (RTC)”
Reworked Section 25.5.6 “Updating Time/Calendar”
Reworked Figure 25-7 “Calibration Circuitry Waveforms”
AD index ‘7’ replaced with generic ‘n’ in Section 25.5.8 “Waveform Generation”
Updated Figure 25-8 “Waveform Generation for ADC Trigger Event”
Section 25.6.2 “RTC Mode Register”:
- updated descriptions of fields OUT0 and OUT1 - added fields TPERIOD and THIGH
Section 27. “Low Power Asynchronous Receiver (RXLP)”
Pin/signal name “LPRXD” changed to “RXD”
Section 29. “Clock Generator”
Section 29.2 “Embedded Characteristics”: AUDIOPLLCK changed to AUDIOPLLCLK
Figure 29-1 “Clock Generator Block Diagram”: lines changed to arrows for OSCSEL to multiplexer, for MOSCSEL to multiplexer, and for PLLADIV2 to “PLLA and Divider” block
Figure 29-5 “Divider and PLLA Block Diagram”: added PLLADIV2 divider
Updated Section 29.8 “Audio PLL”
Section 30. “Power Management Controller (PMC)”
AUDIOPLLCK changed to AUDIOPLLCLK in Section 30.15 “Programmable Clock Controller” and Section 30.16 “Generic Clock Controller”
Figure 30-1 “General Clock Block Diagram”: added PLLA block; repositioned PLLACK signal; at bottom of diagram “PCKx” changed to “PCKx (to pads)”
Table 30-3 “Register Mapping”: PMC_AUDIO_PLL0 reset value ‘0x0000_0000’ changed to ‘0x0000_00D0’
Section 30.22.11 “PMC Master Clock Register”: updated CSS field description
Section 30.22.13 “PMC Programmable Clock Register”: added addresses 0xF0014044 and 0xF0014048; updated CSS field description
Section 30.22.39 “PMC Audio PLL Control Register 0”: added fields DCO_FILTER (bits 29:28), DCO_GAIN (bits 27:24) and PLLFLT (bits 7:4)
Section 30.22.40 “PMC Audio PLL Control Register 1”: updated DIV field description
Section 31. “Parallel Input/Output Controller (PIO)”
Section 31.4.2 “External Interrupt Lines”: “are generally multiplexed” changed to “are multiplexed”
Section 31.5 “Functional Description”: removed entire section “Peripheral Muxing Example”
Table 31-4 “Register Mapping”:
- added reset value for PIO_CFGR, PIO_ODSR, PIO_IMR, S_PIO_CFGR, S_PIO_ODSR and S_PIO_IMR - “PIO I/O Freeze Register” corrected to “PIO I/O Freeze Configuration Register”
- defined offset range 0x400–0x4FC as reserved
- reserved offset range 0x5E8–0x5F8 changed to 0x5E8–0x5FC
- “Secure PIO I/O Freeze Register” corrected to “Secure PIO I/O Freeze Configuration Register”
Removed duplicated or invalid addresses in Section 31.7.1 “PIO Mask Register”, Section 31.7.2 “PIO Configuration Register”, Section 31.7.3 “PIO Pin Data Status Register”, Section 31.7.4 “PIO Lock Status Register”, Section 31.7.5 “PIO Set Output Data Register”, and Section 31.7.6 “PIO Clear Output Data Register”
Section 31.7.7 “PIO Output Data Status Register”: removed duplicated or invalid addresses; access “Read-only or Read/Write” corrected to “Read/Write”
Removed duplicated or invalid addresses in Section 31.7.8 “PIO Interrupt Enable Register”, Section 31.7.9 “PIO Interrupt Disable Register”, Section 31.7.10 “PIO Interrupt Mask Register”, and Section 31.7.11 “PIO Interrupt Status Register”
Section 31.7.12 “PIO I/O Freeze Configuration Register”: corrected title (was “PIO Freeze Configuration Register”); removed duplicated or invalid addresses; access “Read/Write” corrected to “Write-only”
Removed duplicated or invalid addresses in Section 31.7.15 “Secure PIO Mask Register”, Section 31.7.16 “Secure PIO Configuration Register”, Section 31.7.17 “Secure PIO Pin Data Status Register”, Section 31.7.18 “Secure PIO Lock Status Register”, Section 31.7.19 “Secure PIO Set Output Data Register” and Section 31.7.20 “Secure PIO Clear Output Data Register”
Section 31.7.21 “Secure PIO Output Data Status Register”: removed duplicated or invalid addresses; access “Read-only or Read/Write” corrected to “Read/Write”
Removed duplicated or invalid addresses in Section 31.7.22 “Secure PIO Interrupt Enable Register”, Section 31.7.23 “Secure PIO Interrupt Disable Register”, Section 31.7.24 “Secure PIO Interrupt Mask Register”, and Section 31.7.25 “Secure PIO Interrupt Status Register”
Section 31.7.29 “Secure PIO I/O Freeze Configuration Register”: corrected title (was “Secure PIO Freeze Configuration Register”); removed duplicated or invalid addresses; access “Read/Write” corrected to “Write-only”
Section 31.7.30 “Secure PIO Slow Clock Divider Debouncing Register”: added sentence about register write protection
Section 32. “External Memories”
Table 32-1 “DDR/LPDDR I/O Lines Description”: updated DDR_VREF function description
Section 33. “Multiport DDR-SDRAM Controller (MPDDRC)”
Section 33.4.1 “Low-power DDR1-SDRAM Initialization”: in first paragraph, removed content about configuring register SFR_DDRCFG
Section 33.6 “Software Interface/SDRAM Organization, Address Mapping”: modified description of Interleaved mode (“at each SDRAM end page” corrected to “at each DDRSDRAM end of page”)
Harmonized register naming throughout Section 33.7 “AHB Multiport DDR-SDRAM Controller (MPDDRC) User Interface”
Removed all MPDDRC DLL registers (offset range 0x100–0x158 now reserved)
Section 33.7.3 “MPDDRC Configuration Register”: modified description of DECOD bit value ‘1’ (“at each SDRAM end page” corrected to “at each DDR-SDRAM end of page”)
Section 33.7.12 “MPDDRC I/O Calibration Register”: updated RZQ values in RDIV field description
Section 34. “Static Memory Controller (SMC)”
Section 34.17.3 “NFC Initialization”: instances of “rbn” changed to “Ready/Busy”
Section 34.20.3 “NFC Status Register”: bit RB_EDGE3 (bit 27) replaced by RB_EDGE0 (bit 24); updated RB_RISE and RB_FALL bit descriptions
Bit RB_EDGE3 (bit 27) replaced by RB_EDGE0 (bit 24) in Section 34.20.4 “NFC Interrupt Enable Register”, Section 34.20.5 “NFC Interrupt Disable Register” and Section 34.20.6 “NFC Interrupt Mask Register”
Deleted invalid addresses in Section 34.20.30 “PMECC Error Location SIGMA0 Register” and Section 34.20.31 “PMECC Error Location SIGMAx Register”
Section 34.20.32 “PMECC Error Location x Register”: register index “x=0..23” corrected to “x=0..31”
Section 34.20.36 “Timings Register”: removed RBNSEL field
Section 35. “DMA Controller (XDMAC)”
Added XDMAC_CCx.CSIZE configuration to Table 35-2 “DMA Channels Definition (XDMAC0)” and Table 35-3 “DMA Channels Definition (XDMAC1)”
Table 35-5 “Register Mapping”:
- XDMAC_GCFG access Read-only corrected to Read/Write
- XDMAC_GWAC access Read-only corrected to Read/Write
Section 35.9.2 “XDMAC Global Configuration Register”: access Read-only corrected to Read/Write
Section 35.9.3 “XDMAC Global Weighted Arbiter Configuration Register”: access Read-only corrected to Read/Write
Section 36. “LCD Controller (LCDC)”
Updated ”Section 36.2 “Embedded Characteristics”
Updated Section 36.6.1.1 “Pixel Clock Period Configuration”
Section 37. “Ethernet MAC (GMAC)”
Table 37-1 “GMAC Connections in Different Modes”: added table Note on GTXCK
Updated Section 37.5.3 “Interrupt Sources”
Section 37.7.1.2 “Receive Buffer List” and Section 37.7.1.3 “Transmit Buffer List”: added note at end of sections on queue pointer intilaization
Section 37.8.107 “GMAC Transmit Buffer Queue Base Address Register Priority Queue x” and Section 37.8.108 “GMAC Receive Buffer Queue Base Address Register Priority Queue x”: changed sentence on register initialization
Section 39. “USB Host High Speed Port (UHPHS)”
Section 39.2 “Embedded Characteristics”: “X Hosts (A and B) High Speed (EHCI)” corrected to “2 Hosts (A and B) High Speed (EHCI)”
Table 39-2 “Register Mapping”: inserted reserved offset 0x0C
Section 39.7.19 “EHCI: REG06 - AHB Error Status”: instances of “INSNREG[8:4]” changed to “INSNREG06[8:4]”
Section 40. “Audio Class D Amplifier (CLASSD)”
Section 40.2 “Embedded Characteristics”: DSP clock frequency “11.289 MHz” corrected to “11.2896 MHz”
Section 40.5.2 “Power Management”: field name “NOVRLAP” corrected to “NOVRVAL”
Figure 40-21 “Use Case 4B: Stereo Audio DAC With Passive Low Pass Filter and Single-ended Outputs”: changed title (was “Use Case 4B: Stereo Audio DAC With Passive Low Pass Filter and Differential Outputs”)
Section 42. “Synchronous Serial Controller (SSC)”
Figure 42-19 “Interrupt Block Diagram”: “RXSYNC” renamed to “RXSYN”; “TXSYNC” renamed to “TXSYN”
Section 42.8.10 “Register Write Protection”: in first sentence, “AIC behavior” corrected to “SSC behavior”
Section 43. “Two-wire Interface (TWIHS)”
Section 43.6.3.10 “SMBus Mode”: Deleted “A dedicated bus line, SMBALERT, allows a slave to get a master attention” from listed exceptions
Section 43.6.5.6 “SMBus Mode”: Deleted “A dedicated bus line, SMBALERT, allows a slave to get a master attention” from listed exceptions
Deleted note about debugger read access in Section 43.7.6 “TWIHS Status Register”, Section 43.7.13 “TWIHS Receive Holding Register” and Section 43.7.25 “TWIHS Write Protection Status Register”
Section 44. “Flexible Serial Communication Controller (FLEXCOM)”
Section 44.7.1.2 “Fractional Baud Rate in Asynchronous Mode”: in first paragraph, deleted sentence “This feature is only available when using USART Normal mode.”
Figure 44-8 “Preamble Patterns, Default Polarity Assumed”: instances of “8 bit width” changed to “8-bit”
Figure 44-11 “Asynchronous Start Detection”: added missing arrowheads
Section 44.7.3.11 “Receiver Timeout”: removed redundant paragraphs on STTTO and RETTO; reworded two bullets
Section 44.7.4 “ISO7816 Mode”: at end of second paragraph, “value 0x5 for protocol T = 1” changed to “value 0x6 for protocol T = 1”
Section 44.7.4.2 “Protocol T = 0”: reworded content under “Receive NACK Inhibit”
Section 44.7.7 “USART Comparison Function on Received Character”: modified information about the CMPMODE bit
Table 44-18 “Register Mapping”: added TWI SleepWalking Matching Register (FLEX_TWI_SWMR)
Section 44.10.41 “USART Write Protection Mode Register”: rephrased WPEN bit description
Corrected order of all sections from Section 44.10.66 “TWI Interrupt Enable Register” to Section 44.10.76 “TWI SleepWalking Matching Register”
Section 44.10.76 “TWI SleepWalking Matching Register”: added addresses
Section 46. “Serial Peripheral Interface (SPI)”
Figure 46-1 “Block Diagram”: added GCLK output from PMC to SPI
Modified transmission condition description in Section 46.7.3 “Master Mode Operations”
Section 46.7.4 “SPI Slave Mode”: added sentence about NSS rising between characters
Section 46.7.5 “SPI Comparison Function on Received Character”: in seventh paragraph, added “if SleepWalking mode is disabled” to sentence “The comparison trigger event is...”
Updated Section 46.7.8 “Register Write Protection”
Section 46.8.2 “SPI Mode Register”: added bits BRSRCCLK (Bit Rate Source Clock) and LSBHALF (LSB Timing Selection); updated description of field DLYBCS
Section 46.8.12 “SPI Chip Select Register”: updated description of fields CSNAAT, SCBR, DLYBS and DLYBCT
Section 47. “Quad Serial Peripheral Interface (QSPI)”
Section 47.2 “Embedded Characteristics”: added bullet “Interface to Serial Flash Memories Operating in Single Data Rate or Double Data Rate Modes”
Section 47. “Quad Serial Peripheral Interface (QSPI)” (cont’d)
NSS renamed to QCS in Figure 47-2 “QSPI Transfer Format (QSPI_SCR.CPHA = 0, 8 bits per transfer)” and Figure 47-3 “QSPI Transfer Format (QSPI_SCR.CPHA = 1, 8 bits per transfer)”
Section 47.7.2 “QSPI Mode Register”: added note “This field is forced to LASTXFER when SMM is written to ‘1’ to CSMODE field description; modified equation in description of fields DLYBCT and DLYCS
Section 47.7.5 “QSPI Status Register”: updated descriptions of bits CSR and INSTRE
Section 47.7.9 “QSPI Serial Clock Register”: modified equation in description of fields SCBR and DLYBS
Section 48. “Secure Digital Multimedia Card Controller (SDMMC)”
Added Section 48.3 “Embedded Features for SDMMC0 and SDMMC1”
Figure 48-1 “Block Diagram”: added two notes
Table 48-3 “Register Mapping”: updated SDMMC_APSR reset value (SDMMC0 different from SDMMC1)
Section 48.13.18 “SDMMC Software Reset Register”: updated SWRSTCMD bit description
Section 48.13.58 “SDMMC Calibration Control Register”: in CNTVAL field description, “tSTARTUP = ...” corrected to “tSTARTUP = 2 µs”
Section 49. “Image Sensor Controller (ISC)”
Added Section 49.4 “Product Dependencies”
Table 49-18 “Register Mapping”: defined offset range 0x404–0x40C as reserved
Section 50. “Controller Area Network (MCAN)”
“GCLK3” changed to “GCLK” in Section 50.3 “Block Diagram” and Section 50.4.2 “Power Management”
Added Table 50-2 “Peripheral IDs”
Updated Section 50.5.1.3 “CAN FD Operation”
Section 50.5.1.4 “Transmitter Delay Compensation”: modified title (was “Transceiver Delay Compensation”); revised content
Section 50.5.1.5 “Restricted Operation Mode”: added ‘Note’
Section 50.5.3 “Timeout Counter”: “baud rate” changed to “bit rate” in ‘Note’
Section 50.5.4.1 “Acceptance Filtering”: “described in Section” corrected to “described in “Rx FIFO Overwrite Mode”
Updated Figure 50-5 “Standard Message ID Filter Path”and Figure 50-6 “Extended Message ID Filter Path”
Updated register names in Figure 50-7 “Rx FIFO Status” and Figure 50-8 “Rx FIFO Overflow Handling”
Section 50.5.7.2 “Rx Buffer and FIFO Element”: “R1 Bit 21 FDF: Extended Data Length” renamed to “R1 Bit 21 FDF: FD Format”
Section 50.5.7.4 “Tx Event FIFO Element”: “E1 Bit 21 FDF: Extended Data Length” renamed to “E1 Bit 21 FDF: FD Format”
Table 50-14 “Register Mapping”:
- deleted row “0x00–0x04 / Reserved”
- “Fast Bit Timing and Prescaler Register” renamed to “Data Bit Timing and Prescaler Register”
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Section 50.6.4 “MCAN Data Bit Timing and Prescaler Register”: changed name (was “MCAN Fast Bit Timing and Prescaler Register”); field FBRP replaced by field DBRP
Section 50.6.7 “MCAN CC Control Register”: updated descriptions of fields FDOE, BRSE, PXHD and EFB; removed NISO bit
Section 50.6.8 “MCAN Nominal Bit Timing and Prescaler Register”: “NBRP: Nominal Baud Rate Prescaler” changed to “NBRP: Nominal Bit Rate Prescaler”
Section 50.6.9 “MCAN Timestamp Counter Configuration Register”: updated TSS field description
Section 50.6.10 “MCAN Timestamp Counter Value Register”: updated TSC field description
Section 50. “Controller Area Network (MCAN)” (cont’d)
Section 50.6.20 “MCAN Global Filter Configuration”: added details on register description; updated ANFE and ANFS field descriptions.
Added details on register description in Section 50.6.21 “MCAN Standard ID Filter Configuration” and Section 50.6.22 “MCAN Extended ID Filter Configuration”
Section 50.6.24 “MCAN High Priority Message Status”: updated description of MSI field value ‘1’
Section 51. “Timer Counter (TC)”
Replaced TIOA, TIOB, TCLK with TIOAx, TIOBx, TCLKx
Table 51-1 “Timer Counter Clock Assignment”: updated definitions
Section 51.6.3 “Clock Selection”: updated bullet “Internal clock signals”, updated notes 1 and 2
Section 51.6.9 “Transfer with DMAC in Capture Mode”: updated title (added “in Capture Mode”)
Updated Figure 51-5 “Example of Transfer with DMAC in Capture Mode”
Section 51.6.16.4 “Position and Rotation Measurement”: updated text in first paragraph
Added Section 51.6.16.6 “Detecting a Missing Index Pulse”
Updated TCCLKS field description in Section 51.7.2 “TC Channel Mode Register: Capture Mode” and Section 51.7.3 “TC Channel Mode Register: Waveform Mode”
Section 53. “Pulse Width Modulation Controller (PWM)”
Throughout, “PWMTRG” and “EXTTRG” renamed to “PWMEXTRG”
Table 53-2 “I/O Lines”: “PWMEXTRG0” and “PWMEXTRG1” renumbered to “PWMEXTRG1” and “PWMEXTRG2”
Updated Section “Recoverable Fault”
Updated Figure 53-1 “Pulse Width Modulation Controller Block Diagram” and added note below figure
Updated Figure 53-16 “Fault Protection”
Section 54. “Secure Fuse Controller (SFC)”
Table 54-1 “Register Mapping”: removed reset value from SFC_IER and SFC_IDR (both registers are write-only)
Section 55. “Integrity Check Monitor (ICM)”
Table 55-8 “Register Mapping”: ICM_SR access “Write-only” corrected to “Read-only”
Section 57. “Advanced Encryption Standard (AES)”
Table 57-5 “Register Mapping”: AES_ALPHAR[0..3] access “Write” corrected to “Write-only”
Section 57.5.20 “AES Alpha Word Register x”: access “Write” corrected to “Write-only”
Section 59. “Triple Data Encryption Standard (TDES)”
Section 59.4.1 “Operating Modes”: deleted sentence “The OFB and CFB modes of operation are only available if 2-key mode is selected (KEYMOD = 1 in TDES_MR).”
Section 59.4.3 “Last Output Data Mode”: deleted sentence “No more Output Data Register reads are necessary between consecutive encryptions/decryptions (see Section 59.4.3 “Last Output Data Mode”).”
Section 59.5.2 “TDES Mode Register”: in OPMOD field description, deleted sentence “The OFB and CFB modes of operation are only available if 2-key mode is selected (KEYMOD = 1).”
Section 61. “Security Module”
Updated Figure 61-2 “Security Module Internal Memory Map”
Section 62. “Analog-to-Digital Converter (ADC)”
Section 62.1 “Description”:
- deleted sentence “A digital error correction circuit based on the multi-bit redundant signed digit (RSD) algorithm is implemented to reduce INL and DNL errors.”
- deleted sentence “Finally, the user can configure ADC timings, such as startup time and tracking time.”
Updated Section 62.2 “Embedded Characteristics”
Updated Figure 62-1 “Analog-to-Digital Converter Block Diagram”
Revised Section 62.5 “Product Dependencies”
Revised Section 62.6.1 “Analog-to-Digital Conversion”
Updated Section 62.6.3 “ADC Reference Voltage” and Section 62.6.4 “Conversion Resolution”
Updated Section 62.6.7 “Conversion Triggers”
Section 62.6.9 “Comparison Window”: in fourth paragraph, instance of “ADC_SR” corrected to “ADC_ISR”
Section 62.6.10 “Differential and Single-ended Input Modes”: changed title (was “Differential Inputs”) and revised content
Updated Section 62.6.11 “ADC Timings”, Section 62.6.12 “Last Channel Specific Measurement Trigger”, Section 62.6.13 “Enhanced Resolution Mode and Digital Averaging Function” and Section 62.6.14 “Automatic Error Correction”
Instances of GND renamed to GNDANA in Figure 62-15 “Touchscreen Switches Implementation”, Figure 62-18 “Touchscreen Switches Implementation” and Figure 62-20 “Touchscreen Pen Detect”
Updated Section 62.6.16 “Asynchronous and Partial Wakeup (SleepWalking)”
Section 62.6.17.1 “Classic ADC Channels Only (Touchscreen Disabled)”: changed title (was “Classical ADC Channels Only”)
Section 62.6.19 “Register Write Protection”: updated list of protectable registers
Table 62-8 “Register Mapping”:
- defined 0x48 as reserved - added row 0x4C / Channel Offset Register / ADC_COR - added offset 0x7C for ADC_CDR11 - defined offset range 0x80–0x90 as reserved - added row 0x94 / Analog Control Register / ADC_ACR - defined offset range 0xC4–0xD0 as reserved - added row 0xD4 / Correction Values Register / ADC_CVR - added row 0xD8 / Channel Error Correction Register / ADC_CECR - added row 0xDC / Touchscreen Correction Values Register / ADC_TSCVR - defined offset 0xE0 as reserved
Section 62.7.2 “ADC Mode Register”: updated TRACKIM field description
Added LCCHG (Last Channel Change) bit in Section 62.7.9 “ADC Interrupt Enable Register”, Section 62.7.10 “ADC Interrupt Disable Register”, Section 62.7.11 “ADC Interrupt Mask Register” and Section 62.7.12 “ADC Interrupt Status Register”
Section 62.7.13 “ADC Last Channel Trigger Mode Register”: updated CMPMOD field description
Section 62.7.16 “ADC Extended Mode Register”: updated CMPMODE field description; added descriptions for fields OSR ASTE
Section 62.7.18 “ADC Channel Offset Register”: added address; removed bits OFF11:OFF0 from bitmap; modified DIFFx field description
Section 62.7.20 “ADC Analog Control Register”: added address; added IBCTL field
Section 62.7.25 “ADC Trigger Register”: added sentence about write protection
Removed Section “Correction Select Register”
Added sentence about write protection in Section 62.7.26 “ADC Correction Values Register” and Section 62.7.27 “ADC Channel Error Correction Register”
Added Section 62.7.28 “ADC Touchscreen Correction Values Register”
Section 63. “Electrical Characteristics”
“ADVREFP” corrected to “ADVREF”
Section 63.2 “DC Characteristics”: in first sentence, “TA = -40°C to +85°C” changed to “TA = -40°C to +105°C”
Added Table 63-2 “Recommended Thermal Operating Conditions”
Updated Section 63.4 “Active Mode”
Table 63-8 “Low-power Mode Configuration Summary”: updated values for ‘Consumption’ and ‘Wakeup Time’
Updated Section 63.5.6 “Low-power Consumption Versus Modes”
Table 63-9 “Typical Power Consumption in Idle Mode: AMP2”: updated consumption values
Table 63-10 “VDDCORE Power Consumption in Ultra Low-power Mode: AMP2”: updated consumption values; updated wakeup time for ULP1 Fast Wakeup mode
Table 63-11 “Typical Power Consumption for Backup Mode”: updated consumption values
Updated Table 63-12 “Processor Clock Waveform Parameters” and Table 63-13 “Master Clock Waveform Parameters”
Updated Section 63.7.1 “Main Oscillator Characteristics”
Table 63-17 “12 MHz RC Oscillator Characteristics”: updated startup time values
Updated Section 63.7.3 “32.768 kHz Crystal Oscillator Characteristics”
Updated Table 63-23 “Audio PLL Characteristics”
Section 63.10 “ADC Characteristics”: deleted sentence “The VREFN pin must be connected to ground.”
Table 63-25 “Power Supply Characteristics”: updated Analog Current Consumption value for Fast Wakeup mode
Table 63-26 “ADVREF Electrical Characteristics”: “VREFP” corrected to “ADVREF”; updated Current value
Section 63.10.4.1 “Differential Mode (12-bit mode)” and Section 63.10.4.2 “Single-ended Mode (12-bit mode)”: in equation, “VVREFP” corrected to “VADVREF”
Section 63.10.4.4 “Gain and Offset Errors”: “VVREFP” corrected to “VADVREF”
Table 63-27 “ADC Timing Characteristics”: updated footnote
Added Table 63-32 “ADC Analog Input Characteristics”
Table 63-37 “VDDCORE Power-On Reset Characteristics”: updated Hysteresis Voltage values
Section 63.14.1 “Maximum SPI Frequency”: updated values in “Master Read Mode” and “Slave Write Mode”
Revised Section 63.18 “MPDDRC Timings”
Corrected CKI values in Figure 63-33 “SSC Transmitter, TK and TF in Input”, Figure 63-35 “SSC Receiver, RK in Input and RF in Output”, Figure 63-36 “SSC Receiver, RK and RF in Output” and Figure 63-38 “Minimum and Maximum Access Time of Output Signals”
Section 65. “Schematic Checklist”
Figure 65-1 “1.2V, 1.35V/1.5V, 2V, 2.5V, 3.3V Power Supplies Schematics(1)”: GNDHSIC changed to GNDUTMIC
Table 65-1 “Power Supply Connections”: updated GNDUTMIC row; removed GNDHSIC row; in second footnote, “microcontroller” changed to “microprocessor”
Table 65-2 “Clock, Oscillator and PLL Connections”: “(internal 32-kHz RC oscillator) changed to “(internal 64 kHz RC oscillator)”
Section 65.5.1 “How to Define the Oscillator Load Capacitance”: instances of “32-KHz Oscillator” changed to “32.768 kHz Oscillator”
Added Section 65.14.6 “QSPI Pull-up Resistors”
Updated Section 67. “Ordering Information”
Section 68. “Errata”
Updated and reorganized content (errata now collected in Section 68.1 “Errata - SAMA5D2 MRL-B Parts” and Section 68.2 “Errata - SAMA5D2 MRL-A Parts”)

Minor formatting and editorial changes throughout

“Introduction”

Updated listed DDR memories

“Features”

Frequency of digital fractional PLL for audio “11.289 MHz” corrected to “11.2896 MHz”

“Two 64-bit, 16-channel DMA controllers” changed to “51 DMA Channels including two 16-channel 64-bit Central DMA Controllers”

Section 1. “Description”

Updated description of Low-power modes

Section 2. “Configuration Summary”

“Class D amplifier” changed to “stereo Class D amplifier”

Updated text at end of section

Section 3. “Block Diagram”

Figure 3-1 “SAMA5D2 Series Block Diagram”: added ISC_MSK input; updated description of crystal oscillators; “PWMEXTRIG0-1” renumbered to “PWMEXTRG1–2”

Added note “See Section 35. “DMA Controller (XDMAC)” for peripheral connections to DMA.”

Section 4. “Signal Description”

Table 4-1 “Signal Description List”: NRST signal function “Microcontroller Reset” changed to “Microprocessor Reset”; “PWMEXTRG0-1” renumbered to “PWMEXTRG1–2”; “Self-refresh mode” changed to “Backup Self-refresh mode” in DDR_CKE comments

Section 5. “Package and Pinout”

Separated content into Section 5.1 “Packages” and Section 5.2 “Pinouts”

Table 5-2 “Pin Description (SAMA5D21, SAMA5D22, SAMA5D24, SAMA5D26, SAMA5D27, SAMA5D28A)”: “ADVREFP” corrected to “ADVREF”; “PWMEXTRG0” and “PWMEXTRG1” renumbered to “PWMEXTRG1” and “PWMEXTRG2”; removed empty function cells for primary signals PA30, PA31, and PB0–PB7; removed “SEC, FILTER” from “Reset State” column header; added footnote on reset states

Added Table 5-3 “Pin Description (SAMA5D23 pins different from those in SAMA5D21/SAMA5D2)” and Table 5-4 “Pin Description (SAMA5D28B pins different from those in SAMA5D28A)”

Section 6. “Power Considerations”

Table 6-1 “SAMA5D2 Power Supplies”: updated rows VDDUTMIC, VDDHSIC and VDDOSC

Section 6.4.1 “VDDBU Power Architecture”: reworded second paragraph and deleted “typically less than 2 µA”

Section 7. “Memories”

Section 7.2.1 “External Bus Interface”: “The slew rates are determined by programming the SFR_EBICFG bit in SFR registers” changed to “The drive levels are configured with the DRIVEx field in the EBI Configuration Register (SFR_EBICFG)”

Section 8. “Event System”

Section 8-1 “Real-time Event Mapping List”: instance of “ADC_ADTRG” corrected to “ADTRG”

Section 9. “System Controller”

Section 9.1 “Power-On Reset”: “dedicated to VDDBU, VDDIOP and VDDCORE” changed to “dedicated to monitoring VDDBU, VDDIOP and VDDCORE”

Section 10. “Peripherals”

Table 10-1 “Peripheral identifiers”: in ‘Instance Name’ column, renamed CAN0 and CAN1 to MCAN0 and MCAN1

Section 10.4 “Peripheral Clock Types”: in SLOW_CLOCK description, “32768-Hz crystal oscillator or by the on-chip 32-kHz RC oscillator” changed to “32.768 kHz crystal oscillator or by the on-chip 64 kHz RC oscillator”

Section 11. “Chip Identifier (CHIPID)”

Updated Table 11-1 “SAMA5D2 Chip ID Registers”

Section 13. “L2 Cache Controller (L2CC)”

Table 13-2 “Register Mapping”: reset value 0x0000_0000 changed to 0x0000_0111 for L2CC_TRCR and L2CC_DRCR

Section 14. “Debug and Test Features”

Table 14-1 “Debug and Test Pin List”: NRST pin function “Microcontroller Reset” changed to “Microprocessor Reset”

Section 15. “Standard Boot Strategies”

“Boot Sequence Control Register (BSCR)” renamed to “Boot Sequence Controller Configuration Register”

Section 15.1 “Description”: “This microcontroller can be configured” changed to “This microprocessor can be configured”

Figure 15-10 “Galois Field Table Mapping”: modified Galois field table offsets

Section 15.4.2 “Boot Sequence Controller Configuration Register”: added address

Section 15.4.3 “Boot Configuration Word”: added reference to “Customer Fuse Matrix”

Added Section 15.4.6.5 “QSPI Flash Boot”

Table 15-3 “PIO Driven during Boot Program Execution”: NAND Flash PIO line PIOC17 changed to PIOB0

Section 18. “Special Function Registers (SFR)”

Table 18-1 “Register Mapping”: removed EBI Configuration Register / SFR_EBICFG (offset 0x40 now reserved)

Section 18.3.1 “DDR Configuration Register”: added note

Removed section “EBI Configuration Register”

Section 21. “Watchdog Timer (WDT)”

Section 21.4 “Functional Description”: in eighth paragraph, “To prevent a software deadlock that continuously triggers the watchdog, the reload of the watchdog must occur...” changed to “The reload of the watchdog must occur...”

Section 25. “Real-time Clock (RTC)”

Reworked Section 25.5.6 “Updating Time/Calendar”

Reworked Figure 25-7 “Calibration Circuitry Waveforms”

AD index ‘7’ replaced with generic ‘n’ in Section 25.5.8 “Waveform Generation”

Updated Figure 25-8 “Waveform Generation for ADC Trigger Event”

Section 25.6.2 “RTC Mode Register”:

- updated descriptions of fields OUT0 and OUT1

- added fields TPERIOD and THIGH

Section 27. “Low Power Asynchronous Receiver (RXLP)”

Pin/signal name “LPRXD” changed to “RXD”

Section 29. “Clock Generator”

Section 29.2 “Embedded Characteristics”: AUDIOPLLCK changed to AUDIOPLLCLK

Figure 29-1 “Clock Generator Block Diagram”: lines changed to arrows for OSCSEL to multiplexer, for MOSCSEL to multiplexer, and for PLLADIV2 to “PLLA and Divider” block

Figure 29-5 “Divider and PLLA Block Diagram”: added PLLADIV2 divider

Updated Section 29.8 “Audio PLL”

Section 30. “Power Management Controller (PMC)”

AUDIOPLLCK changed to AUDIOPLLCLK in Section 30.15 “Programmable Clock Controller” and Section 30.16 “Generic Clock Controller”

Figure 30-1 “General Clock Block Diagram”: added PLLA block; repositioned PLLACK signal; at bottom of diagram “PCKx” changed to “PCKx (to pads)”

Table 30-3 “Register Mapping”: PMC_AUDIO_PLL0 reset value ‘0x0000_0000’ changed to ‘0x0000_00D0’

Section 30.22.11 “PMC Master Clock Register”: updated CSS field description

Section 30.22.13 “PMC Programmable Clock Register”: added addresses 0xF0014044 and 0xF0014048; updated CSS field description

Section 30.22.39 “PMC Audio PLL Control Register 0”: added fields DCO_FILTER (bits 29:28), DCO_GAIN (bits 27:24) and PLLFLT (bits 7:4)

Section 30.22.40 “PMC Audio PLL Control Register 1”: updated DIV field description

Section 31. “Parallel Input/Output Controller (PIO)”

Section 31.4.2 “External Interrupt Lines”: “are generally multiplexed” changed to “are multiplexed”

Section 31.5 “Functional Description”: removed entire section “Peripheral Muxing Example”

Table 31-4 “Register Mapping”:

- added reset value for PIO_CFGR, PIO_ODSR, PIO_IMR, S_PIO_CFGR, S_PIO_ODSR and S_PIO_IMR

- “PIO I/O Freeze Register” corrected to “PIO I/O Freeze Configuration Register”

- defined offset range 0x400–0x4FC as reserved

- reserved offset range 0x5E8–0x5F8 changed to 0x5E8–0x5FC

- “Secure PIO I/O Freeze Register” corrected to “Secure PIO I/O Freeze Configuration Register”

Removed duplicated or invalid addresses in Section 31.7.1 “PIO Mask Register”, Section 31.7.2 “PIO Configuration Register”, Section 31.7.3 “PIO Pin Data Status Register”, Section 31.7.4 “PIO Lock Status Register”, Section 31.7.5 “PIO Set Output Data Register”, and Section 31.7.6 “PIO Clear Output Data Register”

Section 31.7.7 “PIO Output Data Status Register”: removed duplicated or invalid addresses; access “Read-only or Read/Write” corrected to “Read/Write”

Removed duplicated or invalid addresses in Section 31.7.8 “PIO Interrupt Enable Register”, Section 31.7.9 “PIO Interrupt Disable Register”, Section 31.7.10 “PIO Interrupt Mask Register”, and Section 31.7.11 “PIO Interrupt Status Register”

Section 31.7.12 “PIO I/O Freeze Configuration Register”: corrected title (was “PIO Freeze Configuration Register”); removed duplicated or invalid addresses; access “Read/Write” corrected to “Write-only”

Removed duplicated or invalid addresses in Section 31.7.15 “Secure PIO Mask Register”, Section 31.7.16 “Secure PIO Configuration Register”, Section 31.7.17 “Secure PIO Pin Data Status Register”, Section 31.7.18 “Secure PIO Lock Status Register”, Section 31.7.19 “Secure PIO Set Output Data Register” and Section 31.7.20 “Secure PIO Clear Output Data Register”

Section 31.7.21 “Secure PIO Output Data Status Register”: removed duplicated or invalid addresses; access “Read-only or Read/Write” corrected to “Read/Write”

Removed duplicated or invalid addresses in Section 31.7.22 “Secure PIO Interrupt Enable Register”, Section 31.7.23 “Secure PIO Interrupt Disable Register”, Section 31.7.24 “Secure PIO Interrupt Mask Register”, and Section 31.7.25 “Secure PIO Interrupt Status Register”

Section 31.7.29 “Secure PIO I/O Freeze Configuration Register”: corrected title (was “Secure PIO Freeze Configuration Register”); removed duplicated or invalid addresses; access “Read/Write” corrected to “Write-only”

Section 31.7.30 “Secure PIO Slow Clock Divider Debouncing Register”: added sentence about register write protection

Section 32. “External Memories”

Table 32-1 “DDR/LPDDR I/O Lines Description”: updated DDR_VREF function description

Section 33. “Multiport DDR-SDRAM Controller (MPDDRC)”

Section 33.4.1 “Low-power DDR1-SDRAM Initialization”: in first paragraph, removed content about configuring register SFR_DDRCFG

Section 33.6 “Software Interface/SDRAM Organization, Address Mapping”: modified description of Interleaved mode (“at each SDRAM end page” corrected to “at each DDRSDRAM end of page”)

Harmonized register naming throughout Section 33.7 “AHB Multiport DDR-SDRAM Controller (MPDDRC) User Interface”

Removed all MPDDRC DLL registers (offset range 0x100–0x158 now reserved)

Section 33.7.3 “MPDDRC Configuration Register”: modified description of DECOD bit value ‘1’ (“at each SDRAM end page” corrected to “at each DDR-SDRAM end of page”)

Section 33.7.12 “MPDDRC I/O Calibration Register”: updated RZQ values in RDIV field description

Section 34. “Static Memory Controller (SMC)”

Section 34.17.3 “NFC Initialization”: instances of “rbn” changed to “Ready/Busy”

Section 34.20.3 “NFC Status Register”: bit RB_EDGE3 (bit 27) replaced by RB_EDGE0 (bit 24); updated RB_RISE and RB_FALL bit descriptions

Bit RB_EDGE3 (bit 27) replaced by RB_EDGE0 (bit 24) in Section 34.20.4 “NFC Interrupt Enable Register”, Section 34.20.5 “NFC Interrupt Disable Register” and Section 34.20.6 “NFC Interrupt Mask Register”

Deleted invalid addresses in Section 34.20.30 “PMECC Error Location SIGMA0 Register” and Section 34.20.31 “PMECC Error Location SIGMAx Register”

Section 34.20.32 “PMECC Error Location x Register”: register index “x=0..23” corrected to “x=0..31”

Section 34.20.36 “Timings Register”: removed RBNSEL field

Section 35. “DMA Controller (XDMAC)”

Added XDMAC_CCx.CSIZE configuration to Table 35-2 “DMA Channels Definition (XDMAC0)” and Table 35-3 “DMA Channels Definition (XDMAC1)”

Table 35-5 “Register Mapping”:

- XDMAC_GCFG access Read-only corrected to Read/Write

- XDMAC_GWAC access Read-only corrected to Read/Write

Section 35.9.2 “XDMAC Global Configuration Register”: access Read-only corrected to Read/Write

Section 35.9.3 “XDMAC Global Weighted Arbiter Configuration Register”: access Read-only corrected to Read/Write

Section 36. “LCD Controller (LCDC)”

Updated ”Section 36.2 “Embedded Characteristics”

Updated Section 36.6.1.1 “Pixel Clock Period Configuration”

Section 37. “Ethernet MAC (GMAC)”

Table 37-1 “GMAC Connections in Different Modes”: added table Note on GTXCK

Updated Section 37.5.3 “Interrupt Sources”

Section 37.7.1.2 “Receive Buffer List” and Section 37.7.1.3 “Transmit Buffer List”: added note at end of sections on queue pointer intilaization

Section 37.8.107 “GMAC Transmit Buffer Queue Base Address Register Priority Queue x” and Section 37.8.108 “GMAC Receive Buffer Queue Base Address Register Priority Queue x”: changed sentence on register initialization

Section 39. “USB Host High Speed Port (UHPHS)”

Section 39.2 “Embedded Characteristics”: “X Hosts (A and B) High Speed (EHCI)” corrected to “2 Hosts (A and B) High Speed (EHCI)”

Table 39-2 “Register Mapping”: inserted reserved offset 0x0C

Section 39.7.19 “EHCI: REG06 - AHB Error Status”: instances of “INSNREG[8:4]” changed to “INSNREG06[8:4]”

Section 40. “Audio Class D Amplifier (CLASSD)”

Section 40.2 “Embedded Characteristics”: DSP clock frequency “11.289 MHz” corrected to “11.2896 MHz”

Section 40.5.2 “Power Management”: field name “NOVRLAP” corrected to “NOVRVAL”

Figure 40-21 “Use Case 4B: Stereo Audio DAC With Passive Low Pass Filter and Single-ended Outputs”: changed title (was “Use Case 4B: Stereo Audio DAC With Passive Low Pass Filter and Differential Outputs”)

Section 42. “Synchronous Serial Controller (SSC)”

Figure 42-19 “Interrupt Block Diagram”: “RXSYNC” renamed to “RXSYN”; “TXSYNC” renamed to “TXSYN”

Section 42.8.10 “Register Write Protection”: in first sentence, “AIC behavior” corrected to “SSC behavior”

Section 43. “Two-wire Interface (TWIHS)”

Section 43.6.3.10 “SMBus Mode”: Deleted “A dedicated bus line, SMBALERT, allows a slave to get a master attention” from listed exceptions

Section 43.6.5.6 “SMBus Mode”: Deleted “A dedicated bus line, SMBALERT, allows a slave to get a master attention” from listed exceptions

Deleted note about debugger read access in Section 43.7.6 “TWIHS Status Register”, Section 43.7.13 “TWIHS Receive Holding Register” and Section 43.7.25 “TWIHS Write Protection Status Register”

Section 44. “Flexible Serial Communication Controller (FLEXCOM)”

Section 44.7.1.2 “Fractional Baud Rate in Asynchronous Mode”: in first paragraph, deleted sentence “This feature is only available when using USART Normal mode.”

Figure 44-8 “Preamble Patterns, Default Polarity Assumed”: instances of “8 bit width” changed to “8-bit”

Figure 44-11 “Asynchronous Start Detection”: added missing arrowheads

Section 44.7.3.11 “Receiver Timeout”: removed redundant paragraphs on STTTO and RETTO; reworded two bullets

Section 44.7.4 “ISO7816 Mode”: at end of second paragraph, “value 0x5 for protocol T = 1” changed to “value 0x6 for protocol T = 1”

Section 44.7.4.2 “Protocol T = 0”: reworded content under “Receive NACK Inhibit”

Section 44.7.7 “USART Comparison Function on Received Character”: modified information about the CMPMODE bit

Table 44-18 “Register Mapping”: added TWI SleepWalking Matching Register (FLEX_TWI_SWMR)

Section 44.10.41 “USART Write Protection Mode Register”: rephrased WPEN bit description

Corrected order of all sections from Section 44.10.66 “TWI Interrupt Enable Register” to Section 44.10.76 “TWI SleepWalking Matching Register”

Section 44.10.76 “TWI SleepWalking Matching Register”: added addresses

Section 46. “Serial Peripheral Interface (SPI)”

Figure 46-1 “Block Diagram”: added GCLK output from PMC to SPI

Modified transmission condition description in Section 46.7.3 “Master Mode Operations”

Section 46.7.4 “SPI Slave Mode”: added sentence about NSS rising between characters

Section 46.7.5 “SPI Comparison Function on Received Character”: in seventh paragraph, added “if SleepWalking mode is disabled” to sentence “The comparison trigger event is...”

Updated Section 46.7.8 “Register Write Protection”

Section 46.8.2 “SPI Mode Register”: added bits BRSRCCLK (Bit Rate Source Clock) and LSBHALF (LSB Timing Selection); updated description of field DLYBCS

Section 46.8.12 “SPI Chip Select Register”: updated description of fields CSNAAT, SCBR, DLYBS and DLYBCT

Section 47. “Quad Serial Peripheral Interface (QSPI)”

Section 47.2 “Embedded Characteristics”: added bullet “Interface to Serial Flash Memories Operating in Single Data Rate or Double Data Rate Modes”

Section 47. “Quad Serial Peripheral Interface (QSPI)” (cont’d)

NSS renamed to QCS in Figure 47-2 “QSPI Transfer Format (QSPI_SCR.CPHA = 0, 8 bits per transfer)” and Figure 47-3 “QSPI Transfer Format (QSPI_SCR.CPHA = 1, 8 bits per transfer)”

Section 47.7.2 “QSPI Mode Register”: added note “This field is forced to LASTXFER when SMM is written to ‘1’ to CSMODE field description; modified equation in description of fields DLYBCT and DLYCS

Section 47.7.5 “QSPI Status Register”: updated descriptions of bits CSR and INSTRE

Section 47.7.9 “QSPI Serial Clock Register”: modified equation in description of fields SCBR and DLYBS

Section 48. “Secure Digital Multimedia Card Controller (SDMMC)”

Added Section 48.3 “Embedded Features for SDMMC0 and SDMMC1”

Figure 48-1 “Block Diagram”: added two notes

Table 48-3 “Register Mapping”: updated SDMMC_APSR reset value (SDMMC0 different from SDMMC1)

Section 48.13.18 “SDMMC Software Reset Register”: updated SWRSTCMD bit description

Section 48.13.58 “SDMMC Calibration Control Register”: in CNTVAL field description, “tSTARTUP = ...” corrected to “tSTARTUP = 2 µs”

Section 49. “Image Sensor Controller (ISC)”

Added Section 49.4 “Product Dependencies”

Table 49-18 “Register Mapping”: defined offset range 0x404–0x40C as reserved

Section 50. “Controller Area Network (MCAN)”

“GCLK3” changed to “GCLK” in Section 50.3 “Block Diagram” and Section 50.4.2 “Power Management”

Added Table 50-2 “Peripheral IDs”

Updated Section 50.5.1.3 “CAN FD Operation”

Section 50.5.1.4 “Transmitter Delay Compensation”: modified title (was “Transceiver Delay Compensation”); revised content

Section 50.5.1.5 “Restricted Operation Mode”: added ‘Note’

Section 50.5.3 “Timeout Counter”: “baud rate” changed to “bit rate” in ‘Note’

Section 50.5.4.1 “Acceptance Filtering”: “described in Section” corrected to “described in “Rx FIFO Overwrite Mode”

Updated Figure 50-5 “Standard Message ID Filter Path”and Figure 50-6 “Extended Message ID Filter Path”

Updated register names in Figure 50-7 “Rx FIFO Status” and Figure 50-8 “Rx FIFO Overflow Handling”

Section 50.5.7.2 “Rx Buffer and FIFO Element”: “R1 Bit 21 FDF: Extended Data Length” renamed to “R1 Bit 21 FDF: FD Format”

Section 50.5.7.4 “Tx Event FIFO Element”: “E1 Bit 21 FDF: Extended Data Length” renamed to “E1 Bit 21 FDF: FD Format”

Table 50-14 “Register Mapping”:

- deleted row “0x00–0x04 / Reserved”

- “Fast Bit Timing and Prescaler Register” renamed to “Data Bit Timing and Prescaler Register”

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Section 50.6.4 “MCAN Data Bit Timing and Prescaler Register”: changed name (was “MCAN Fast Bit Timing and Prescaler Register”); field FBRP replaced by field DBRP

Section 50.6.7 “MCAN CC Control Register”: updated descriptions of fields FDOE, BRSE, PXHD and EFB; removed NISO bit

Section 50.6.8 “MCAN Nominal Bit Timing and Prescaler Register”: “NBRP: Nominal Baud Rate Prescaler” changed to “NBRP: Nominal Bit Rate Prescaler”

Section 50.6.9 “MCAN Timestamp Counter Configuration Register”: updated TSS field description

Section 50.6.10 “MCAN Timestamp Counter Value Register”: updated TSC field description

Section 50. “Controller Area Network (MCAN)” (cont’d)

Section 50.6.20 “MCAN Global Filter Configuration”: added details on register description; updated ANFE and ANFS field descriptions.

Added details on register description in Section 50.6.21 “MCAN Standard ID Filter Configuration” and Section 50.6.22 “MCAN Extended ID Filter Configuration”

Section 50.6.24 “MCAN High Priority Message Status”: updated description of MSI field value ‘1’

Section 51. “Timer Counter (TC)”

Replaced TIOA, TIOB, TCLK with TIOAx, TIOBx, TCLKx

Table 51-1 “Timer Counter Clock Assignment”: updated definitions

Section 51.6.3 “Clock Selection”: updated bullet “Internal clock signals”, updated notes 1 and 2

Section 51.6.9 “Transfer with DMAC in Capture Mode”: updated title (added “in Capture Mode”)

Updated Figure 51-5 “Example of Transfer with DMAC in Capture Mode”

Section 51.6.16.4 “Position and Rotation Measurement”: updated text in first paragraph

Added Section 51.6.16.6 “Detecting a Missing Index Pulse”

Updated TCCLKS field description in Section 51.7.2 “TC Channel Mode Register: Capture Mode” and Section 51.7.3 “TC Channel Mode Register: Waveform Mode”

Section 53. “Pulse Width Modulation Controller (PWM)”

Throughout, “PWMTRG” and “EXTTRG” renamed to “PWMEXTRG”

Table 53-2 “I/O Lines”: “PWMEXTRG0” and “PWMEXTRG1” renumbered to “PWMEXTRG1” and “PWMEXTRG2”

Updated Section “Recoverable Fault”

Updated Figure 53-1 “Pulse Width Modulation Controller Block Diagram” and added note below figure

Updated Figure 53-16 “Fault Protection”

Section 54. “Secure Fuse Controller (SFC)”

Table 54-1 “Register Mapping”: removed reset value from SFC_IER and SFC_IDR (both registers are write-only)

Section 55. “Integrity Check Monitor (ICM)”

Table 55-8 “Register Mapping”: ICM_SR access “Write-only” corrected to “Read-only”

Section 57. “Advanced Encryption Standard (AES)”

Table 57-5 “Register Mapping”: AES_ALPHAR[0..3] access “Write” corrected to “Write-only”

Section 57.5.20 “AES Alpha Word Register x”: access “Write” corrected to “Write-only”

Section 59. “Triple Data Encryption Standard (TDES)”

Section 59.4.1 “Operating Modes”: deleted sentence “The OFB and CFB modes of operation are only available if 2-key mode is selected (KEYMOD = 1 in TDES_MR).”

Section 59.4.3 “Last Output Data Mode”: deleted sentence “No more Output Data Register reads are necessary between consecutive encryptions/decryptions (see Section 59.4.3 “Last Output Data Mode”).”

Section 59.5.2 “TDES Mode Register”: in OPMOD field description, deleted sentence “The OFB and CFB modes of operation are only available if 2-key mode is selected (KEYMOD = 1).”

Section 61. “Security Module”

Updated Figure 61-2 “Security Module Internal Memory Map”

Section 62. “Analog-to-Digital Converter (ADC)”

Section 62.1 “Description”:

- deleted sentence “A digital error correction circuit based on the multi-bit redundant signed digit (RSD) algorithm is implemented to reduce INL and DNL errors.”

- deleted sentence “Finally, the user can configure ADC timings, such as startup time and tracking time.”

Updated Section 62.2 “Embedded Characteristics”

Updated Figure 62-1 “Analog-to-Digital Converter Block Diagram”

Revised Section 62.5 “Product Dependencies”

Revised Section 62.6.1 “Analog-to-Digital Conversion”

Updated Section 62.6.3 “ADC Reference Voltage” and Section 62.6.4 “Conversion Resolution”

Updated Section 62.6.7 “Conversion Triggers”

Section 62.6.9 “Comparison Window”: in fourth paragraph, instance of “ADC_SR” corrected to “ADC_ISR”

Section 62.6.10 “Differential and Single-ended Input Modes”: changed title (was “Differential Inputs”) and revised content

Updated Section 62.6.11 “ADC Timings”, Section 62.6.12 “Last Channel Specific Measurement Trigger”, Section 62.6.13 “Enhanced Resolution Mode and Digital Averaging Function” and Section 62.6.14 “Automatic Error Correction”

Instances of GND renamed to GNDANA in Figure 62-15 “Touchscreen Switches Implementation”, Figure 62-18 “Touchscreen Switches Implementation” and Figure 62-20 “Touchscreen Pen Detect”

Updated Section 62.6.16 “Asynchronous and Partial Wakeup (SleepWalking)”

Section 62.6.17.1 “Classic ADC Channels Only (Touchscreen Disabled)”: changed title (was “Classical ADC Channels Only”)

Section 62.6.19 “Register Write Protection”: updated list of protectable registers

Table 62-8 “Register Mapping”:

- defined 0x48 as reserved

- added row 0x4C / Channel Offset Register / ADC_COR

- added offset 0x7C for ADC_CDR11

- defined offset range 0x80–0x90 as reserved

- added row 0x94 / Analog Control Register / ADC_ACR

- defined offset range 0xC4–0xD0 as reserved

- added row 0xD4 / Correction Values Register / ADC_CVR

- added row 0xD8 / Channel Error Correction Register / ADC_CECR

- added row 0xDC / Touchscreen Correction Values Register / ADC_TSCVR

- defined offset 0xE0 as reserved

Section 62.7.2 “ADC Mode Register”: updated TRACKIM field description

Added LCCHG (Last Channel Change) bit in Section 62.7.9 “ADC Interrupt Enable Register”, Section 62.7.10 “ADC Interrupt Disable Register”, Section 62.7.11 “ADC Interrupt Mask Register” and Section 62.7.12 “ADC Interrupt Status Register”

Section 62.7.13 “ADC Last Channel Trigger Mode Register”: updated CMPMOD field description

Section 62.7.16 “ADC Extended Mode Register”: updated CMPMODE field description; added descriptions for fields OSR ASTE

Section 62.7.18 “ADC Channel Offset Register”: added address; removed bits OFF11:OFF0 from bitmap; modified DIFFx field description

Section 62.7.20 “ADC Analog Control Register”: added address; added IBCTL field

Section 62.7.25 “ADC Trigger Register”: added sentence about write protection

Removed Section “Correction Select Register”

Added sentence about write protection in Section 62.7.26 “ADC Correction Values Register” and Section 62.7.27 “ADC Channel Error Correction Register”

Added Section 62.7.28 “ADC Touchscreen Correction Values Register”

Section 63. “Electrical Characteristics”

“ADVREFP” corrected to “ADVREF”

Section 63.2 “DC Characteristics”: in first sentence, “TA = -40°C to +85°C” changed to “TA = -40°C to +105°C”

Added Table 63-2 “Recommended Thermal Operating Conditions”

Updated Section 63.4 “Active Mode”

Table 63-8 “Low-power Mode Configuration Summary”: updated values for ‘Consumption’ and ‘Wakeup Time’

Updated Section 63.5.6 “Low-power Consumption Versus Modes”

Table 63-9 “Typical Power Consumption in Idle Mode: AMP2”: updated consumption values

Table 63-10 “VDDCORE Power Consumption in Ultra Low-power Mode: AMP2”: updated consumption values; updated wakeup time for ULP1 Fast Wakeup mode

Table 63-11 “Typical Power Consumption for Backup Mode”: updated consumption values

Updated Table 63-12 “Processor Clock Waveform Parameters” and Table 63-13 “Master Clock Waveform Parameters”

Updated Section 63.7.1 “Main Oscillator Characteristics”

Table 63-17 “12 MHz RC Oscillator Characteristics”: updated startup time values

Updated Section 63.7.3 “32.768 kHz Crystal Oscillator Characteristics”

Updated Table 63-23 “Audio PLL Characteristics”

Section 63.10 “ADC Characteristics”: deleted sentence “The VREFN pin must be connected to ground.”

Table 63-25 “Power Supply Characteristics”: updated Analog Current Consumption value for Fast Wakeup mode

Table 63-26 “ADVREF Electrical Characteristics”: “VREFP” corrected to “ADVREF”; updated Current value

Section 63.10.4.1 “Differential Mode (12-bit mode)” and Section 63.10.4.2 “Single-ended Mode (12-bit mode)”: in equation, “VVREFP” corrected to “VADVREF”

Section 63.10.4.4 “Gain and Offset Errors”: “VVREFP” corrected to “VADVREF”

Table 63-27 “ADC Timing Characteristics”: updated footnote

Added Table 63-32 “ADC Analog Input Characteristics”

Table 63-37 “VDDCORE Power-On Reset Characteristics”: updated Hysteresis Voltage values

Section 63.14.1 “Maximum SPI Frequency”: updated values in “Master Read Mode” and “Slave Write Mode”

Revised Section 63.18 “MPDDRC Timings”

Corrected CKI values in Figure 63-33 “SSC Transmitter, TK and TF in Input”, Figure 63-35 “SSC Receiver, RK in Input and RF in Output”, Figure 63-36 “SSC Receiver, RK and RF in Output” and Figure 63-38 “Minimum and Maximum Access Time of Output Signals”

Section 65. “Schematic Checklist”

Figure 65-1 “1.2V, 1.35V/1.5V, 2V, 2.5V, 3.3V Power Supplies Schematics(1)”: GNDHSIC changed to GNDUTMIC

Table 65-1 “Power Supply Connections”: updated GNDUTMIC row; removed GNDHSIC row; in second footnote, “microcontroller” changed to “microprocessor”

Table 65-2 “Clock, Oscillator and PLL Connections”: “(internal 32-kHz RC oscillator) changed to “(internal 64 kHz RC oscillator)”

Section 65.5.1 “How to Define the Oscillator Load Capacitance”: instances of “32-KHz Oscillator” changed to “32.768 kHz Oscillator”

Added Section 65.14.6 “QSPI Pull-up Resistors”

Updated Section 67. “Ordering Information”

Section 68. “Errata”

Updated and reorganized content (errata now collected in Section 68.1 “Errata - SAMA5D2 MRL-B Parts” and Section 68.2 “Errata - SAMA5D2 MRL-A Parts”)