70.6 Revision DS60001476D - 02/2020

NAND Flash PMECC Register: updated nbSectorPerPage description.

Updated Wake-Up Inputs.

SHDW_SR: added note.

SHDW_WUIR: added WKUPT1 detail.

Replaced “SLCK” by “slow clock” throughout.

Updated Reference Clock.

• Alarm
• RTC Internal Free-Running Counter Error Checking
• Gregorian and Persian Modes
• RTC Accurate Clock Calibration

Updated

• Time/Calendar Update Timing Diagram
• Gregorian and Persian Modes Update Sequence
• UTC Time Update Timing Diagram
• UTC Mode Update Sequence.

RTC_CR: updated UPDCAL and UPDTIM bit descriptions.

RTC_SCCR: updated description.

Updated the table Clock Assignments with new rows for UART, TWI and SPI.

PMC_PCKx: modified description of PRES field.

Block Diagram: updated description.

DDR2-SDRAM Initialization: added TRFC constraint content

Corrected Interleaved Mapping DDR-SDRAM Configuration Mapping: 8K Rows, 512/1024/2048 Columns, 4 Banks

MPDDRC_CR: updated NDQS bit description.

MPDDRC_LPR: updated CHG_FRQ bit description.

MPDDRC_TPR1: TRFC field name corrected from "Row Cycle Delay" to "Row Refresh cycle".

Description: replaced AHB with “system bus”.

Modified:

• 4:2:2 Planar Mode Chrominance Memory Mapping, Little Endian Organization for Byte 0x0, 0x1, 0x2, 0x3
• 4:2:0 Planar Mode Chrominance Memory Mapping, Little Endian Organization for Byte 0x0, 0x1, 0x2, 0x3
• 4:2:0 Planar Mode Chrominance Memory Mapping, Little Endian Organization for Byte 0x4, 0x5, 0x6, 0x7
• Base Layer with Window Overlay Optimization

Added figure in Pixel Clock Period Configuration.

Changed all occurrences of GEMAC to GMAC.

References to MDIO pin modified to GMDIO pin.

Timestamp Unit: updated paragraph on GTSUCOMP and added figure “GTSUCOMP Connection”.

GMAC_RRE.RXRER: modified description.

GMAC_NSR: added note for the register reset value.

GMAC_CBSCR: Corrected inverted bits.

GMAC_EFTSH: updated offset.

- GMAC_ISRPQx

- GMAC_TBQBAPQx

- GMAC_RBQBAPQx

- GMAC_RBSRPQx

- GMAC_IERPQx

- GMAC_IDRPQx

- GMAC_IMRPQx

Description: added a note.

Embedded Characteristics: modified first item in the list.

CLASSD Block Diagram: added note.

SSC_TFMR: updated DATDEF bit description

Updated Master Performs a General Call.

Updated TWIHS Read Operation with Multiple Data Bytes + Write Operation with Multiple Data Bytes (Sr).

TWIHS_CWGR: updated CLDIV and CHDIV bit descriptions.

Added detail: “This register reads "0" if the FIFO is disabled (see TWI_CR to enable/disable the internal FIFO)” in:

• TWIHS_FMR
• TWIHS_FLR
• TWIHS_FSR
• TWIHS_FIMR

Updated FLEXCOM Block Diagram.

Updated Master Performs a General Call.

TWI Compatibility with I2C Standard: updated with Fast Mode Plus and High Speed Mode.

TWI/SMBus Characteristics: updated for Fast Mode Plus and High-speed mode.

Modes of Operation: updated for High-speed mode.

Master Mode: updated Definition, Master Transmitter Mode and Master Receiver Mode.

Updated TWI Read Operation with Multiple Data Bytes + Write Operation with Multiple Data Bytes (Sr).

FLEX_US_CR: updated REQCLR description.

FLEX_TWI_FILTR: removed bit PADFCFG.

FLEX_US_RTOR: updated TO field description.

FLEX_US_IDR: corrected OVRE bit description.

FLEX_TWI_CWGR: updated CLDIV and CHDIV bit descriptions.

Added note in FLEX_US_FMR, FLEX_US_FLR, FLEX_US_FIMR, FLEX_SPI_SR, FLEX_SPI_FMR, FLEX_SPI_FLR, FLEX_TWI_FMR, FLEX_TWI_FLR, FLEX_TWI_FSR and FLEX_TWI_FMR.

UART_IMR: TXRDY description: typo fixed (Disable replaced with Mask).

Instruction Frame Transmission: updated all flowcharts.

QSPI_MR: updated NBBITS field description.

SDMMC_CA0R: updated SLTYPE field description and updated note.

SDMMC_AESR: updated ERRST field description.

SDMMC_CA1R: updated note.

SDMMC_NISTR (SD_SDIO): corrected CINT bit description.

SDMMC_MCCAR: updated note.

TC_EMRx: updated TRIGSRCB field description.

Updated Block Diagram.

Block Diagram and Channel Block Diagram: removed all occurrences of APB.

Updated Fault Protection.

Comparator: updated formulae for duty cycle for left-aligned and center-aligned.

Updated Fuse Functions.

SFC_SR: index 16 now ‘reserved’.

Embedded Characteristics: added a bullet for new feature.

Added Temporary Secured Storage for Keys.

Updated 59.4.2 Operating Modes and added new detail on initialization vectors.

AES_MR: in OPMOD description, added new detail on initialization vectors.

AES_IVRx: added new detail on initialization vectors.

Updated:

• Description
• Processing Period
• Double Input Buffer

SHA_IDATARx: renamed register from “SHA Input Data x Register” to “SHA Input Data Register x”

61.2 Embedded Characteristics: added bullet for new feature.

Updated TDES_MR.LOD = 1.

Added “Temporary Secured Storage for Keys”.

TDES_CR: modified SWRST description (removed “hardware”)

Corrected field description in TDES_KEYxWRy, TDES_IDATARx, TDES_ODATARx and TDES_IVRx.

Updated Description.

Updated Last Channel Specific Measurement Trigger.

Updated Sequence of Consecutive ADC Conversions with TRACKTIM = 15

Updated Sequence of Consecutive ADC Conversions with TRACKTIM = 0

ADC_CHSR: updated CHx bit description

Added note to table PLLA Characteristics.