| Section 6. “Package and Pinout” |
| Table 6-2 Pin Description: added notes (2) and
(3). |
| Table 6-3 Pin Description (SAMA5D23 pins different from
those in Table 6-2 “Pin Description”): added note (2). |
| Table 6-4 Pin Description (SAMA5D28B/C pins different
from those in Table 6-2 “Pin Description”): added note (2). |
| Section 7. “Power Considerations” |
| Updated Figure 7-1 “Recommended Powerup Sequence” and
Table 7-2 “Powerup Timing Specification”. |
| Section 16. “Standard Boot Strategies” |
| Updated Section 16.4.7.3 “SDCard / e.MMC Boot”. |
| Reworked Section 16.4.7.6 “QSPI NOR Flash Boot for MRL
C”. |
| Section 29. “Peripheral Touch Controller
(PTC)” |
| - Replaced "Peripheral Touch Controller" with
"Peripheral Touch Controller Subsystem". |
| - Changed "PTC_IRQ_EVT" to "PTC_IRQ". |
| - Replaced "PIO" and "IO" with "GPIO". |
| Updated: |
| - Figure 29-1. "PTC Block Diagram" |
| - Section 29.2 “Embedded Characteristics” |
| - Section 29.5.2 “I/O Lines” |
| - Section 29.5.3 “Interrupt Sources” |
| - Section 29.6.2.3 “Firmware in SRAM Code Area” |
| Section 29.5.1 “Power Management”: updated description
of “SLCK”. |
| Section 29.6.3.1 “PTC Digital Controller Operations”:
modified Sensing mode description. |
| Renamed and reworked Section 29.7.1 “PTC Command
Register” and Section 29.7.2 “PTC Interrupt Status Register”. |
| Section 29.7.3 “PTC Enable Register”: removed field
CLR_IRQEN, and replaced field SET_IRQEN with bits IER0, IER1, IER2,
IER3. |
| Renamed the following registers: |
| - “Mode 1: Write Access” to “PTC Command
Register” |
| - “Host Flags” to “PTC Interrupt Status Register” |
| - “Host Flags Control” to “PTC Enable Register” |
| Section 39. “LCD Controller (LCDC)” |
| Corrected Figure 39-1. Block Diagram (added “PP Layer”
block). |
| Section 66. “Electrical Characteristics” |
| Added Section 66.10 ”PTC Characteristics”. |
| Section 66.5.3.1 “ULP0 Mode”: updated steps (5) and
(6). |
| Table 66-9 “Typical Peripheral Power Consumption by
Peripheral in Active Mode”: corrected UHPHS consumption value from "12
*MCK + 4900*DR" to "12 *MCK + 490*DR" and UDPHS consumption value from
“10 *MCK + 2060*DR” to “10 *MCK + 206*DR” |
| Table 66-13 “VDDCORE Power Consumption in Ultra
Low-power Mode: AMP2”: removed ULP0 512 Hz row. |
| Section 68. “Schematic Checklist” |
| Removed Section 68.3 “Shutdown Considerations” and
Section 68.4 “Wakeup Considerations” (redundant with content in Section
7. “Power Considerations”). |
| Table 68-1 “Power Supply Connections”: updated VDDCORE
recommended pin connection from “1.08V to 1.32V” to “1.1V to
1.32V”. |
| Table 68-2 “Clock, Oscillator and PLL Connections”:
updated main oscillator recommended pin connection from "Crystals
between 8 and 16 MHz" to "Crystals between 8 and 24 MHz". |
| Table 68-6 “Reset and Test Connections”: updated NRST
recommended pin connection. |
| Section 69. “Marking” |
| Updated marking information. |
| Section 71. “Errata” |
| Added the following issues in Section 71.1 “Errata -
SAMA5D2 MRL C Parts”: |
| Section 71.1.9 “Master CAN-FD Controller (MCAN)” to
Section 71.1.18 “MCAN High Priority Message (HPM)” and Section 71.1.19
“ROM Code: Using JTAG IOSET 4”. |
| Added the following issues in Section 71.2 “Errata -
SAMA5D2 MRL B Parts”: |
| Section 71.2.10 “Master CAN-FD Controller (MCAN)” to
Section 71.2.19 “MCAN High Priority Message (HPM)” and Section 71.2.20
“ROM Code: Using JTAG IOSET 4”. |
| Added the following issues in Section 71.3 “Errata -
SAMA5D2 MRL A Parts”: |
| Section 71.3.26 “Master CAN-FD Controller (MCAN)” to
Section 71.3.35 “MCAN High Priority Message (HPM)” and Section 71.3.36
“ROM Code: Using JTAG IOSET 4”. |
