70.9 Revision DS60001476A

Changes
General
- Template update: Moved from Atmel to Microchip template.
- The datasheet is assigned a new document number (DS60001476) and revision letter is reset to A.
--- Document number DS60001476 revision A corresponds to what would have been 11267 revision F.
- ISBN number assigned.
“Features”: added PTC.
Table 2. “Configuration Summary”: added PTC. Corrected number of Timers.
Section 3. “Block Diagram”
Figure 3-1 “SAMA5D2 Series Block Diagram”: corrected SDMMC signals. Updated peripheral bridge naming. Added PTC. Removed signal names.
Section 4. “Signal Description”
Table 4-1 “Signal Description List”: renamed SDMMCx_VDDSEL to SDMMCx_1V8SEL. Added PTC pins on PD0 to PD18.
Added Section 5. “Safety and Security Features”.
Section 6. “Package and Pinout”
Added Note on IO sets.
Table 6-2 “Pin Description”: for P15/R14 renamed SDMMC0_VDDSEL to SDMMC0_1V8SEL.
Section 7. “Power Considerations”
Table 7-1 “SAMA5D2 Power Supplies”: in VDDBU row, corrected RC Oscillator frequency to 64 kHz.
Section 8. “Memories”
Figure 8-1 “Memory Mapping”: renamed MATRIXx blocks. Added PTC. Renamed TC blocks. Added SYSCWP block.
Section 11. “Peripherals”
Table 11-1 “Peripheral Identifiers”: corrected reference to SDMMC. Assigned ID 58 to Peripheral Touch Controller (PTC).
Section 11.4 “Peripheral Clock Types”: removed clock type HCLOCK and PCLOCK from table.
Section 12. “Chip Identifier (CHIPID)”
Table 12-1 “SAMA5D2 Chip ID Registers”: added chip ids for MRL C revision.
Section 13. “ARM Cortex-A5”
Section 13.4.7.3 “Debug”: updated Note.
Section 16. “Standard Boot Strategies”
Replaced all occurrences of “Spansion” by “Cypress”.
Updated Section 16.3 “Chip Setup”.
Updated Section 16.4.1 “Boot Configuration Word”.
Section 16.4.2 “Boot Sequence Controller Configuration Register”: updated BUREG_VALID bit description.
Added Note to descriptions of SDMMC_0 and SDMMC_1 in Section 16.4.4 “Boot Configuration Word”.
Updated Section 16.4.5 “NVM Boot Sequence” and figures.
Renamed Section 16.4.7.5 “QSPI Flash Boot for MRL A and MRL B”.
Added Section 16.4.7.6 “QSPI Flash Boot for MRL C”.
Updated Section 16.4.8 “Hardware and Software Constraints”:
-- added Table 16-5 “Clock Frequencies during External Memory Boot Sequence”.
-- Table 16-6 “PIO Driven during Boot Program Execution”: renamed SDMMC_VDDSEL to SDMMC0_1V8SEL. Added column “Drive Strength (MRL C only)”.
Section 16.5 “SAM-BA Monitor”: deleted sentence on Main Clock; updated 3rd paragraph.
Updated Section 16.6.1 “Fuse Bit Mapping”.
Section 18. “Matrix (H64MX/H32MX)”
Table 18-5 “List of H32MX Slaves”: added Peripheral Touch Controller (PTC) at Slave 6.
Table 18-6 “Master to Slave Access on H32MX”: added Peripheral Touch Controller (PTC) at Slave 6.
Table 18-9 “Peripheral Identifiers”: added PTC at ID 58.
Section 19. “Special Function Registers (SFR)”
Section 19.3.5 “UTMI Clock Trimming Register”: VBG now 2 bits wide at index [17:16] (was [19:16]).
Section 20. “Special Function Registers Backup (SFRBU)”
Section 20.3.3 “SFRBU DDR BU Mode Control Register” changed occurrences of VCCCORE to VDDCORE.
Section 26. “Real-time Clock (RTC)”
Table 26-1 “Register Mapping”: updated offsets as of 0xCC. Deleted RTC_WPMR at offset 0xE4.
Deleted “Section 25.6.23 RTC Write Protection Mode Register”.
Added Section 27. “System Controller Write Protection (SYSCWP)”.
Added Section 29. “Peripheral Touch Controller (PTC)”.
Section 33. “Power Management Controller (PMC)”
Reorganized order of sub-sections within the chapter.
Updated Figure 33-2 “H32MX 32-bit Matrix Clock Configuration”.
Figure 33-1 “General Clock Block Diagram”: updated PMC_PCR block.
Added Section 33.8 “Core and Bus Independent Clocks for Peripherals”.
Added Section 33.9 “Peripheral and Generic Clock Controller”.
Deleted section “Peripheral Clock Controller”.
Deleted section “Generic Clock Controller”.
Figure 33-10 “Clock Failure Detection (Example)”: corrected CDFEV to CFDEV and CDFS to CFDS.
Section 33.19 “Programming Sequence”: deleted paragraph on DIVA from Step 6.
Section 33.22.10 “PMC Clock Generator PLLA Register”: changed DIVA description for value ‘0’.
Section 35. “External Memories”
Updated Figure 35-2 “MPDDRC Block Diagram”.
Table 35-1 “DDR/LPDDR I/O Lines Description”: DDR_DQS[3:0] and DDR_DQSN[3:0] now type I/O.
Aligned signal names in schematics of Section 35.1 “Multiport DDR-SDRAM Controller (MPDDRC)” with signal names in Table 35-2 “I/O Lines Usage vs Operating Modes”.
Section 36. “Multiport DDR-SDRAM Controller (MPDDRC)”
Section 36.1 “Description”: corrected supported CAS latency.
Section 36.4.1 “Low-power DDR1-SDRAM Initialization”: updated Step 12.
Section 36.4.2 “DDR2-SDRAM Initialization”: updated Step 22.
Section 36.4.3 “Low-power DDR2-SDRAM Initialization”: updated Step 22.
Section 36.4.4 “DDR3-SDRAM/DDR3L-SDRAM Initialization”: updated Step 13.
Section 36.4.5 “Low-power DDR3-SDRAM Initialization”: updated Step 22.
Table 36-1 “CAS Write Latency”: added row for Low-power DDR3-SDRAM. Corrected typo in note.
Table 36-2 “CAS Read Latency”: added row for Low-power DDR3-SDRAM. Corrected typo in note.
Section 36.7.2 “MPDDRC Refresh Timer Register”: updated the method to compute COUNT.
Section 36.7.3 “MPDDRC Configuration Register”: updated NC field description table.
Section 36.7.6 “MPDDRC Timing Parameter 2 Register”: in TRPA description, added “In the case of LPDDR2-SDRAM, this field is equivalent to tRPAB.”
Section 36.7.10 “MPDDRC Low-power DDR2 Low-power DDR3 and DDR3 Calibration and MR4 Register”: in COUNT_CAL field description, added ‘One ZQCS command can effectively correct at least 1.5% of output impedance errors within Tzqcs.’ and ‘TSens and VSens are given by the manufacturer (Output Driver Sensitivity definition). Tdriftrate and Vdriftrate are defined by the end user.’
Section 38. “DMA Controller (XDMAC)”
Added information regarding XDMAC_CC.INITD in Section 38.8 “XDMAC Software Requirements” and Section 38.9.28 “XDMAC Channel x [x = 0..15] Configuration Register”.
Section 38.9.3 “XDMAC Global Weighted Arbiter Configuration Register”: replaced “XDMAC scheduler” with “DMAC scheduler” throughout.
Section 39. “LCD Controller (LCDC)”
Standardized signal names from ‘LCD_XXX’ to ‘LCDXXX’ (‘underscore’ character removed)
Section 39.2 “Embedded Characteristics”: removed “(at synthesis time)” from characteristic “Asynchronous Output Mode Supported”.
Section 40. “Ethernet MAC (GMAC)”
Section 40.2 “Embedded Characteristics”: deleted queue sizes (now found in Table 40-6 “Queue Size”).
Table 40.6.3.9 “Priority Queueing in the DMA”: added Table 40-6 “Queue Size” and updated queue sizes.
Section 40.6.15 “Timestamp Unit”: changed pin reference from “TIOB11/PD22” to “TIOA11/PD21”.
Added Section 40.6.18 “Energy-efficient Ethernet Support”
Updated Section 40.6.19 “802.1Qav Support - Credit-based Shaping”: added definitions of portTransmitRate and IdleSlope; updated content on queue priority management.
Added Section 40.6.20 “LPI Operation in the GMAC”.
Table 40-18 “Register Mapping”: added registers at offsets 0x270 to 0x27C.
Section 40.8.1 “GMAC Network Control Register”: added bit 19: TXLPIEN: Enable LPI Transmission (was ‘reserved’). Added bit description. Changed description of SRTSM bit.
Section 40.8.3 “GMAC Network Status Register”: added bit 7: RXLPIS: LPI Indication (was ‘reserved’). Added bit description.
Added bit 27: RXLPISBC: Receive LPI indication Status Bit Change and bit description and added bit 29: TSUTIMCOMP: TSU timer comparison interrupt and bit description in:
- Section 40.8.10 “GMAC Interrupt Status Register”
- Section 40.8.11 “GMAC Interrupt Enable Register”
- Section 40.8.12 “GMAC Interrupt Disable Register”
- Section 40.8.13 “GMAC Interrupt Mask Register”
Section 40.8.13 “GMAC Interrupt Mask Register”: added bit 26, SRI, and bit 28, WOL, and bit descriptions.
Added following sections:
- Section 40.8.106 “GMAC Received LPI Transitions”
- Section 40.8.107 “GMAC Received LPI Time”
- Section 40.8.108 “GMAC Transmit LPI Transitions”
- Section 40.8.109 “GMAC Transmit LPI Time”
Section 40.8.115 “GMAC Credit-Based Shaping IdleSlope Register for Queue A” and Section 40.8.116 “GMAC Credit-Based Shaping IdleSlope Register for Queue B”: updated example for calculation of IdleSlope.
Section 41. “USB High Speed Device Port (UDPHS)”
Table 41-6 “Register Mapping”: offsets 0xD0 to 0xDC now ‘reserved’.
Deleted internal registers:
- UDPHS Test SOF Counter Register
- UDPHS Test A Counter Register
- UDPHS Test B Counter Register
- UDPHS Test Mode Register
Section 43. “Audio Class D Amplifier (CLASSD)”
Section 43.6.6 “Application Schematics For Use Case Examples”: for Use Case 1, added information on external MOSFET selection.
Section 44. “Inter-IC Sound Controller (I2SC)”
In text, tables and figures, pin names changed to:
- I2SC_MCK
- I2SC_CK
- I2SC_WS
- I2SC_DI
- I2SC_DO
Updated Figure 44-1 “I2SC Block Diagram”.
Section 44.6.1 “Initialization”: added detail on configuring SFR_I2SCLKSEL.
Section 44.6.5 “Serial Clock and Word Select Generation”: updated paragraph on I2SC input clock selection in Master mode.
Updated Figure 44-3 “I2SC Clock Generation”.
Updated figures in Section 44.7 “I2SC Application Examples”.
Section 44.8.2 “I2SC Mode Register”: updated MODE bit description for value ‘1’. Updated IMCKDIV and IMCKMODE field descriptions.
Section 46. “Two-wire Interface (TWIHS)”
Added Section 46.7.2 “TWIHS Control Register (FIFO_ENABLED)”.
Added Section 46.7.8 “TWIHS Status Register (FIFO_ENABLED)”.
Section 47. “Flexible Serial Communication Controller (FLEXCOM)”
Corrected Figure 47-27 “RTS Line Software Control when FLEX_US_MR.USART_MODE = 2”.
Reworked Section 47.7.11 “USART FIFOs”.
Updated Section 47.8.3.5 “Peripheral Selection”.
Reworked Section 47.8.7 “SPI FIFOs”.
Section 47.9.3.9 “SMBus Mode”: corrected typo in SMBEN bit name (was ‘SMEN’).
Created Section 47.9.6 “TWI FIFOs” by merging Section 10.3.15 “TWI Master Mode FIFOs” and Section 10.5.9 “TWI Slave Mode FIFOs”
Section 47.10.43 “SPI Control Register”: updated TXFCLR and RXFCLR bit descriptions.
Section 47.10.50 “SPI Status Register”: updated RDRF and TDRE bit descriptions.
Section 47.10.55 “SPI FIFO Mode Register”: updated TXRDYM description for value ‘1’. Deleted row for value ‘2’. Updated RXRDYM description for value ‘1’ and for value ‘2’.
Added Section 47.10.61 “TWI Control Register (FIFO_ENABLED)”.
Added Section 47.10.67 “TWI Status Register (FIFO ENABLED)”.
Section 49. “Serial Peripheral Interface (SPI)”
Section 49.7.3.5 “Peripheral Selection”: modified sub-section “Variable Peripheral Select Mode”.
Section 49.7.5 “SPI Comparison Function on Received Character”: replace ‘When the CMPMODE bit is cleared in SPI_CMPR’ with ‘When SPI_MR.CMPMODE is cleared’
In Section 49.7.7 “FIFOs” updated:
- Section 49.7.7.1 “Overview”
- Section 49.7.7.2 “Sending Data with FIFO Enabled”
- Section 49.7.7.3 “Receiving Data with FIFO Enabled”
- Section 49.7.7.5 “TXEMPTY, TDRE and RDRF Behavior”
- Section 49.7.7.6 “Single Data Mode”
- Section 49.7.7.7 “Multiple Data Mode”
- “TDRE and RDRF Configuration”
Section 49.8.1 “SPI Control Register”: updated TXFCLR and RXFCLR bit descriptions.
Section 49.8.8 “SPI Status Register”: updated RDRF and TDRE bit descriptions.
Section 49.8.13 “SPI FIFO Mode Register”: updated TXRDYM description for value ‘1’. Deleted row for value ‘2’. Updated RXRDYM description for value ‘1’ and for value ‘2’.
Updated “DMAC” in Section 49.7.7.7 “Multiple Data Mode”.
Section 50. “Quad Serial Peripheral Interface (QSPI)”
Section 50.1 “Description”: added Note on device support.
Removed references to Double Data Rate (DDR) in Section 50.2 “Embedded Characteristics” and Section 50.6.5.2 “Instruction Frame Transmission”.
Section 50.6.5 “QSPI Serial Memory Mode”: updated text on data transfer constraint.
Updated Figure 50-8 “Instruction Frame”.
Figure 50-9 “Instruction Transmission Flow Diagram”:
- Corrected typos:
--- “Wait for flag QSPI_SR.INSTRE ... “ (was “QSPI_CR“)
--- “Wait for flag QSPI_SR.CSR ... “ (was “QSPI_CR“)
- Added new instruction: “Read QSPI_SR (dummy read) to clear QSPI_SR.INSTRE and QSPI_SR.CSR“
Updated Figure 50-10 “Continuous Read Mode”, Figure 50-16 “Instruction Transmission Waveform 6”, Figure 50-17 “Instruction Transmission Waveform 7” and Figure 50-18 “Instruction Transmission Waveform 8”.
Section 51. “Secure Digital MultiMedia Card Controller (SDMMC)”
Section 51.2 “Embedded Characteristics”: updated bullets on support for MMC at default speed and at high speed.
Section 51.3 “Embedded Features for SDMMC0 and SDMMC1”: updated information on SDMMC1.
Section 51.10.1.3 “Boot Procedure, ADMA Mode”: removed note after step j.
Section 51.13.2 “SDMMC Block Size Register” updated BLKSIZE field description.
Section 51.13.9 “SDMMC Present State Register”: updated BUFWREN field description.
Section 51.13.16 “SDMMC Clock Control Register”: updated SDCLKFSEL field description.
Section 51.13.17 “SDMMC Timeout Control Register”: updated equation in DTCVAL field description.
Section 51.13.18 “SDMMC Software Reset Register”: in SWRSTALL field description, updated list of registers cleared to 0 .
Section 51.13.21 “SDMMC Error Interrupt Status Register (SD_SDIO)”: in CURLIM bit description, corrected reference to SDMMC_PCR (was SDMMC_PSR).
Section 51.13.22 “SDMMC Error Interrupt Status Register (e.MMC)”: updated ACMD bit description.
Section 51.13.31 “SDMMC Auto CMD Error Status Register”: changed register access to Read-only.
Section 51.13.32 “SDMMC Host Control 2 Register (SD_SDIO)”: corrected typo in bit 7 name (is SCLKSEL; was SLCKSEL). Updated VS18EN bit description.
Section 51.13.33 “SDMMC Host Control 2 Register (e.MMC)”: corrected typo in bit 7 name (is SCLKSEL; was SLCKSEL).
Section 51.13.41 “SDMMC Preset Value Register”: in Table 51-8 “Preset Value Register Select Condition”: corrected HSEN value in row for High Speed.
Section 51.13.45 “SDMMC e.MMC Control 1 Register”: in DDR bit description Note, replaced ‘HSEN’ with ‘DDR’.
Section 51.13.51 “SDMMC Retuning Counter Value Register”: updated description for TCVAL.
Section 53. “Controller Area Network (MCAN)”
Section 53.1 “Description”: updated information on compliance.
Section 53.4.4 “Address Configuration”: added cross-reference for clarity.
Section 53.5.1.4 “Transmitter Delay Compensation”: changed NTSEG1 to TSEG1.
Section 54. “Timer Counter (TC)”
Table 54-1 “Timer Counter Clock Assignment”: added Note below table.
Section 54.6.16.2 “Input Preprocessing”: removed unit following equation in 3rd paragraph. Added limitation on maximum pulse duration.
Section 54.6.16.4 “Position and Rotation Measurement”: in 3rd paragraph, added “The process must be started by configuring TC_CCR.CLKEN and TC_CCR.SWTRG.”
Section 54.6.16.6 “Detecting a Missing Index Pulse”: corrected value of TC_RC0.RC in example in 2nd paragraph.
Added Section 54.6.16.7 “Detecting Contamination/Dust at Rotary Encoder Low Speed”.
Section 54.7.16 “TC Block Mode Register”: updated MAXFILT field description.
In Section 54.7.17 “TC QDEC Interrupt Enable Register”, Section 54.7.18 “TC QDEC Interrupt Disable Register” and Section 54.7.19 “TC QDEC Interrupt Mask Register”: at index 3, added bit MPE and bit description.
Corrected occurrences of ‘MAXMP’ to ‘MAXCMP’ in Section 54.7.19 “TC QDEC Interrupt Mask Register” and in Section 54.7.20 “TC QDEC Interrupt Status Register”
Section 56. “Pulse Width Modulation Controller (PWM)”
Section 56.6.2.2 “Comparator”: corrected ‘CRPD’ to ‘CPRD’ in formulae.
Table 56-8 “Register Mapping”: modfied offsets for “PWM External Trigger Register 1”, “PWM Leading-Edge Blanking Register 1”, “PWM External Trigger Register 2” and “PWM Leading-Edge Blanking Register 2”.
Section 56.7.43 “PWM Channel Period Register”: corrected ‘CRPD’ to ‘CPRD’ in CPRD description.
Section 56.7.44 “PWM Channel Period Update Register”: corrected ‘CRPDUPD’ to ‘CPRDUPD’ in CPRDUDP description.
Section 57. “Secure Fuse Controller (SFC)”
Removed all occurrences of ‘Atmel reserved area’ ( now just ‘reserved area’).
Modified bit names for APLE and ACE in:
- Section 57.5.3 “SFC Interrupt Enable Register”
- Section 57.5.4 “SFC Interrupt Disable Register”
- Section 57.5.5 “SFC Interrupt Mask Register”
- Section 57.5.6 “SFC Status Register”
Section 58. “Integrity Check Monitor (ICM)”
Updated Section 58.5.5 “ICM Automatic Monitoring Mode”.
Section 58.6.1 “ICM Configuration Register”: updated ASCD description.
Section 59. “Advanced Encryption Standard Bridge (AESB)”
Section 59.1 “Embedded Characteristics”: replaced "12 clock cycles encryption/decryption processing time with a 128-bit cryptographic key" with "10 clock cycles encryption/decryptioninherent processing time".
In Section 59.3.6 “Automatic Bridge Mode”, updated Section 59.3.6.1 “Description”.
Section 60. “Advanced Encryption Standard (AES)”
Replaced references to “keys” and to “AES_KEYWRx registers” with “AES Key Registers”.
Section 60.1 “Description”: corrected index of AES_KEYWR0 registers from 3 to 7.
Section 60.2 “Embedded Characteristics” replaced “12/14/16 Clock Cycles Encryption/Decryption Processing Time” with “10/12/14 Clock Cycles Encryption/Decryption Inherent Processing Time”
Section 61. “Secure Hash Algorithm (SHA)”
Corrected typos in some figures.
Section 61.4.9.1 “Manual Mode”: updated Step 2.
Section 61.5.2 “SHA Mode Register”: updated SMOD bit description.
Section 62. “Triple Data Encryption Standard (TDES)”
Replaced references to “TDES_KEYxWRx registers” with “Key Registers”.
Section 63. “True Random Number Generator (TRNG)”
Section 63.6.1 “TRNG Control Register”: changed field name to WAKEY (was KEY).
Added Section 64. “Security Module (SECUMOD)”.
Section 65. “Analog-to-Digital Converter (ADC)”
Section 65.5.3 “I/O Lines”: “ADC_ADTRG” corrected to “ADTRG”.
Section 65.6.14 “Automatic Error Correction”: added information about ADCMODE field.
Table 65-7 “ADC Running Modes”: updated Offset Error row.
Section 65.6.18 “Fault Event”: reworked and renamed section (was previously “Fault Output”).
Section 65.7.2 “ADC Mode Register”: at index 30, added bit MAXSPEED and bit description
Section 65.7.12 “ADC Interrupt Status Register”: updated LCCHG bit description.
Section 65.7.20 “ADC Analog Control Register”: added Note (1).
Section 66. “Electrical Characteristics”
Table 66-3 “DC Characteristics”: updated min and max valued for low-level and high-level input currents (all pads). Changed ISI_MCK to ISC_MCK.
Updated Table 66-8 “Typical Peripheral Power Consumption by Peripheral in Active Mode” with new column “Clock”.
Table 66-10 “Power Consumption in Active Mode: AMP2”: Removed columns DMIPS and CoreMark.
In Section 66.14 “FLEXCOM Timings”, added Section 66.14.1 “FLEXCOM USART in Asynchronous Modes” and Section 66.14.3 “FLEXCOM TWI Timings”.
In Section 66.14.2 “FLEXCOM SPI Timings”, removed note below all tables from Table 66-52 “FLEXCOM0 in SPI Mode IOSET1 Timings” to Table 66-61 “FLEXCOM4 in SPI Mode IOSET3 Timings”.
Added Section 66.15 “USART in Asynchronous Modes”.
Section 66.16 “SPI Timings”: updated limitation on fSPCK in “Master Read Mode” and “Slave Write Mode”. Removed note below Table 66-63 “SPI0 IOSET1 Timings”, Table 66-64 “SPI0 IOSET2 Timings”, Table 66-65 “SPI1 IOSET1 Timings”, Table 66-66 “SPI1 IOSET2 Timings” and Table 66-67 “SPI1 IOSET3 Timings”.
Section 66.18 “QSPI Timings”: updated limitation on fQSCK in “Master Read Mode”.
Section 66.19.3 “LPDDR1-SDRAM”, Table 66-76 “System Clock Waveform Parameters”: updated min value of tDDRCK for VDDCORE[1.2V, 1.32V].
Section 66.19.4 “LPDDR2/LPDDR3-SDRAM”, Table 66-77 “System Clock Waveform Parameters”: updated min value of tDDRCK for VDDCORE[1.2V, 1.32V].
Section 66.19.5 “DDR3/DDR3L-SDRAM”: updated min values in Table 66-78 “System Clock Waveform Parameters”.
Section 66.23 “ISC Timings”: updated Figure 66-40 “ISC Timing Diagram” and Timings tables.
Section 68. “Schematic Checklist”
Table 68-1 “Power Supply Connections”: removed reference to VCCCORE.
Added Section 68.14.7 “Considerations for PTC Interface”.
Section 70. “Ordering Information”
Updated Table 70-1 “SAMA5D2 Ordering Information” with MRL C ordering codes.
Section 71. “Errata”
Added Section 71.1 “Errata - SAMA5D2 MRL C Parts”.
Section 71.2 “Errata - SAMA5D2 MRL B Parts”: added Section 71.1.1 “GMAC Timestamps and PTP packets”.
Section 71.3 “Errata - SAMA5D2 MRL A Parts”: added
- Section 71.1.1 “GMAC Timestamps and PTP packets”
- Section 71.3.4 “ROM Code: SPI Bootup Frequency”.