47.5.6 Digital Phase Lock Loop (DPLL) Characteristics

Table 47-22. Fractional Digital Phase Lock Loop(2)
SymbolParameter Min.Typ.Max.Unit
FINInput Clock Frequency 32-2000kHz
FOUTOutput Clock FrequencyPL232-96MHz
PL032-48MHz
JpPeriod jitterPL0, Fin = 32 kHz, Fout = 32 MHz -36%
PL2, = 32 kHz, Fout = 32 MHz -26
PL0, Fin = 32 kHz, Fout = 48 MHz -34
PL2, Fin = 32 kHz, Fout = 48 MHz -26
PL2, Fin = 32 kHz, Fout = 96 MHz -34
PL0, Fin = 32 kHz, Fout = 32 MHz -35
PL2, Fin = 32 kHz, Fout = 32 MHz -36
PL0, Fin = 2 MHz, Fout = 48 MHz -57
PL2, Fin = 2 MHz, Fout = 48 MHz -36
PL2, Fin= 2 MHz, Fout= 96 MHz -410
tLOCKLock TimeAfter startup, time to get lock signal Fin = 32 kHz, Fout = 96 MHz-1.11.5ms
After startup, time to get lock signal Fin = 2 MHz, Fout = 96 MHz-2435µs
DutyDuty cycle (1) 405060%
Note:
  1. These values are based on simulation. They are not covered by production test limits or characterization.
  2. These characteristics are applicable only in LDO Regulator mode and with a XOSC or XOSC32K reference.
Table 47-23. Power Consumption(1)(2)
SymbolParameterConditionsTAMin.Typ.Max.Units
IDDCurrent Consumption Fout = 48 MHz (PL0) - VDD = 3.3VMax. 125°C

Typ. 25°C

-339618µA
Fout = 96 MHz (PL2) - VDD = 3.3V-6781005
Note:
  1. These characteristics are only applicable in LDO regulator mode.
  2. These values are based on characterization. They are not covered in test limits in production.