10.2.1.1 SAM L10 User Row
| Bit Pos. | Name | Usage | 
                             Factory Setting  | 
                             Related Peripheral Register  | 
|---|---|---|---|---|
| 2:0 | Reserved | Reserved | Reserved | Reserved | 
| 5:3 | NSULCK | NVM UnLock Bits | 0x7 | NVMCTRL.NSULCK | 
| 6 | Reserved | Reserved | Reserved | Reserved | 
| 12:7 | BOD33_LEVEL | BOD33 threshold level at power-on | 0x6 | SUPC.BOD33 | 
| 13 | BOD33_DIS | BOD33 Disable at power-on | 0x0 | SUPC.BOD33 | 
| 15:14 | BOD33_ACTION | BOD33 Action at power-on | 0x1 | SUPC.BOD33 | 
| 24:16 | BOD12 Calibration Parameters | DO NOT CHANGE(1) | 0x08F | Reserved | 
| 25 | WDT_RUNSTDBY | WDT Runstdby at power-on | 0x0 | WDT.CTRLA | 
| 26 | WDT_ENABLE | WDT Enable at power-on | 0x0 | WDT.CTRLA | 
| 27 | WDT_ALWAYSON | WDT Always-On at power-on | 0x0 | WDT.CTRLA | 
| 31:28 | WDT_PER | WDT Period at power-on | 0xB | WDT.CONFIG | 
| 35:32 | WDT_WINDOW | WDT Window mode time-out at power-on | 0xB | WDT.CONFIG | 
| 39:36 | WDT_EWOFFSET | WDT Early Warning Interrupt Time Offset at power-on | 0xB | WDT.EWCTRL | 
| 40 | WDT_WEN | WDT Timer Window Mode Enable at power-on | 0x0 | WDT.CTRLA | 
| 41 | BOD33_HYST | BOD33 Hysteresis configuration at power-on | 0x0 | SUPC.BOD33 | 
| 255:42 | Reserved | Reserved | Reserved | Reserved | 
CAUTION: 
            
- BOD12 is calibrated in production and its calibration parameters must not be changed to ensure the correct device behavior.
 
| Offset | Bit Pos.  | Name | |||||||
|---|---|---|---|---|---|---|---|---|---|
| 0x00 | 7:0 | BOD33_LEVEL | - | NSULCK | Reserved | ||||
| 0x01 | 15:8 | BOD33_ACTION | BOD33_DIS | BOD33_LEVEL | |||||
| 0x02 | 23:16 | BOD12 Calibration Parameters | |||||||
| 0x03 | 31:24 | WDT_PER | WDT_ALWAYSON | WDT_ENABLE | WDT_RUNSTDBY | BOD12 Calibration Parameters | |||
| 0x04 | 39:32 | WDT_EWOFFSET | WDT_WINDOW | ||||||
| 0x05 | 47:40 | Reserved | BOD33_HYST | WDT_WEN | |||||
| 0x06-0x1F | 255:48 | Reserved | |||||||
