10.2.1.2 SAM L11 User Row
Bit Pos. | Name | Usage |
Factory Setting |
Related Peripheral Register |
---|---|---|---|---|
2:0 | SULCK | NVM Secure Region UnLock Bits | 0x7 | NVMCTRL.SULCK |
5:3 | NSULCK | NVM Non-Secure Region UnLock Bits | 0x7 | NVMCTRL.NSULCK |
6 | Reserved | Reserved | Reserved | Reserved |
12:7 | BOD33_LEVEL | BOD33 threshold level at power-on. | 0x6 | SUPC.BOD33 |
13 | BOD33_DIS | BOD33 Disable at power-on | 0x0 | SUPC.BOD33 |
15:14 | BOD33_ACTION | BOD33 Action at power-on | 0x1 | SUPC.BOD33 |
24:16 | BOD12 Calibration Parameters | Do not change(See Note 1 under Caution) | 0x08F | Reserved |
25 | WDT_RUNSTDBY | WDT Runstdby at power-on | 0x0 | WDT.CTRLA |
26 | WDT_ENABLE | WDT Enable at power-on | 0x0 | WDT.CTRLA |
27 | WDT_ALWAYSON | WDT Always-On at power-on | 0x0 | WDT.CTRLA |
31:28 | WDT_PER | WDT Period at power-on | 0xB | WDT.CONFIG |
35:32 | WDT_WINDOW | WDT Window mode time-out at power-on | 0xB | WDT.CONFIG |
39:36 | WDT_EWOFFSET | WDT Early Warning Interrupt Time Offset at power-on | 0xB | WDT.EWCTRL |
40 | WDT_WEN | WDT Timer Window Mode Enable at power-on | 0x0 | WDT.CTRLA |
41 | BOD33_HYST | BOD33 Hysteresis configuration at power-on | 0x0 | SUPC.BOD33 |
42 | Reserved | Reserved | Reserved | Reserved |
43 | RXN | RAM is eXecute Never | 0x1 | IDAU.SECCTRL |
44 | DXN | Data Flash is eXecute Never | 0x1 | NVMCTRL.SECCTRL |
63:45 | Reserved | Reserved | Reserved | Reserved |
71:64 | AS | Secure Flash (AS region) Size = AS*0x100(5) | 0xFF | IDAU.SCFGA |
77:72 | ANSC | Non-Secure Callable Flash (APPLICATION region) Size = ANSC*0x20 | 0x0 | IDAU.SCFGA |
79:78 | Reserved | Reserved | Reserved | Reserved |
83:80 | DS | Secure Data Flash Size = DS*0x100 | 0x8 | IDAU.SCFGA |
87:84 | Reserved | Reserved | Reserved | Reserved |
94:88 | RS | Secure SRAM Size = RS*0x80 | 0x7F | IDAU.SCFGR |
95 | Reserved | Reserved | Reserved | Reserved |
96 | URWEN | User Row Write Enable | 0x1 | NVMCTRL.SCFGAD |
127:97 | Reserved | Reserved | Reserved | Reserved |
159:128 | NONSECA(1) | Peripherals Non-Secure Status Fuses for Bridge A | 0x0000_0000 | PAC.NONSECA |
191:160 | NONSECB(2, 3) | Peripherals Non-Secure Status Fuses for Bridge B | 0x0000_0000 | PAC.NONSECB |
223:192 | NONSECC | Peripherals Non-Secure Status Fuses for Bridge C | 0x0000_0000 | PAC.NONSECC |
255:224 | USERCRC | CRC of NVM User Row bits 223:64 | 0x8433651E(4) | Boot ROM |
Note:
- The PAC Peripheral is always secured regardless of its bit value
- The IDAU and NVMCTRL peripherals are always secured regardless of their bit values.
- The DSU peripheral is always non-secured regardless of its bit value.
- USERCRC value after a ChipErase_ALL (CE2) is 0x3389CD7C.
- Secure Flash (AS region) = Secure Flash (APPLICATION region) + Non-Secure Callable Flash (APPLICATION region)
CAUTION:
- BOD12 is calibrated in production and its calibration parameters must not be changed to ensure the correct device behavior.
Offset | Bit Pos. |
Name | |||||||
---|---|---|---|---|---|---|---|---|---|
0x00 | 7:0 | BOD33_LEVEL | - | NSULCK | SULCK | ||||
0x01 | 15:8 | BOD33_ACTION | BOD33_DIS | BOD33_LEVEL | |||||
0x02 | 23:16 | BOD12 Calibration Parameters | |||||||
0x03 | 31:24 | WDT_PER | WDT_ALWAYSON | WDT_ENABLE | WDT_RUNSTDBY | BOD12 Calibration Parameters | |||
0x04 | 39:32 | WDT_EWOFFSET | WDT_WINDOW | ||||||
0x05 | 47:40 | Reserved | DXN | RXN | Reserved | BOD33_HYST | WDT_WEN | ||
0x06 | 55:48 | Reserved | |||||||
0x07 | 63:56 | Reserved | |||||||
0x08 | 71:64 | AS | |||||||
0x09 | 79:72 | Reserved | ANSC | ||||||
0x0A | 87:80 | Reserved | DS | ||||||
0x0B | 95:88 | Reserved | RS | ||||||
0x0C | 103:96 | Reserved | URWEN | ||||||
0x0D-0xF | 127:104 | Reserved | |||||||
0x10-0x13 | 159:128 | NONSECA | |||||||
0x14-0x17 | 191:160 | NONSECB | |||||||
0x18-0x1B | 223:192 | NONSECC | |||||||
0x1C-0x1F | 255:224 | USERCRC |