40.6.2.7 Sequential Logic

Each LUT pair can be connected to the internal sequential logic which can be configured to work as D flip flop, JK flip flop, gated D-latch or RS-latch by writing the Sequential Selection bits on the corresponding Sequential Control x register (SEQCTRLx.SEQSEL). Before using sequential logic, the GCLK_CCL clock and optionally each LUT filter or edge detector must be enabled.

Note: While configuring the sequential logic, the even LUT must be disabled. When configured the even LUT must be enabled.

Gated D Flip-Flop (DFF)

When the DFF is selected, the D-input is driven by the even LUT output (LUT(2n)), and the G-input is driven by the odd LUT output (LUT(2n+1)), as shown in the following figure.

Figure 40-13. D Flip Flop

When the even LUT is disabled (LUTCTRL(2n).ENABLE=0), the flip-flop is asynchronously cleared. The reset command (R) is kept enabled for one APB clock cycle. In all other cases, the flip-flop output (OUT) is refreshed on rising edge of the GCLK_CCL, as shown in Table 40-2.

Table 40-2. DFF Characteristics
R G D OUT
1 X X Clear
0 1 1 Set
0 Clear
0 X Hold state (no change)

JK Flip-Flop (JK)

When this configuration is selected, the J-input is driven by the even LUT output (LUT(2n)), and the K-input is driven by the odd LUT output (LUT(2n+1)), as shown in the following figure.

Figure 40-14. JK Flip Flop

When the even LUT is disabled (LUTCTRL(2n).ENABLE=0), the flip-flop is asynchronously cleared. The reset command (R) is kept enabled for one APB clock cycle. In all other cases, the flip-flop output (OUT) is refreshed on rising edge of the GCLK_CCL, as shown in the following table.

Table 40-3. JK Characteristics
R J K OUT
1 X X Clear
0 0 0 Hold state (no change)
0 0 1 Clear
0 1 0 Set
0 1 1 Toggle

Gated D-Latch (DLATCH)

When the DLATCH is selected, the D-input is driven by the even LUT output (LUT(2n)), and the G-input is driven by the odd LUT output (LUT(2n+1)), as shown in the following figure.

Figure 40-15. D-Latch

When the even LUT is disabled (LUTCTRL(2n).ENABLE=0), the latch output will be cleared. The G-input is forced enabled for one more APB clock cycle, and the D-input to zero. In all other cases, the latch output (OUT) is refreshed as shown in the following table.

Table 40-4. D-Latch Characteristics
G D OUT
0 X Hold state (no change)
1 0 Clear
1 1 Set

RS Latch (RS)

When this configuration is selected, the S-input is driven by the even LUT output (LUT(2n)), and the R-input is driven by the odd LUT output (LUT(2n+1)), as shown in the following figure.

Figure 40-16. RS-Latch

When the even LUT is disabled (LUTCTRL(2n).ENABLE=0), the latch output will be cleared. The R-input is forced enabled for one more APB clock cycle and S-input to zero. In all other cases, the latch output (OUT) is refreshed as shown in the following table.

Table 40-5. RS-Latch Characteristics
S R OUT
0 0 Hold state (no change)
0 1 Clear
1 0 Set
1 1 Forbidden state