32.8.10 Control

Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.
Name: CTRL
Offset: 0x24
Reset: 0x00000000
Property: PAC Write-Protection, Secure

Bit 3130292827262524 
 SAMPLING[31:24] 
Access RW/-/RWRW/-/RWRW/-/RWRW/-/RWRW/-/RWRW/-/RWRW/-/RWRW/-/RW 
Reset 00000000 
Bit 2322212019181716 
 SAMPLING[23:16] 
Access RW/-/RWRW/-/RWRW/-/RWRW/-/RWRW/-/RWRW/-/RWRW/-/RWRW/-/RW 
Reset 00000000 
Bit 15141312111098 
 SAMPLING[15:8] 
Access RW/-/RWRW/-/RWRW/-/RWRW/-/RWRW/-/RWRW/-/RWRW/-/RWRW/-/RW 
Reset 00000000 
Bit 76543210 
 SAMPLING[7:0] 
Access RW/-/RWRW/-/RWRW/-/RWRW/-/RWRW/-/RWRW/-/RWRW/-/RWRW/-/RW 
Reset 00000000 

Bits 31:0 – SAMPLING[31:0] Input Sampling Mode

Configures the input sampling functionality of the I/O pin input samplers, for pins configured as inputs via the Data Direction register (DIR).

The input samplers are enabled and disabled in sub-groups of eight. Thus if any pins within a byte request continuous sampling, all pins in that eight pin sub-group will be continuously sampled.

ValueDescription
0 The I/O pin input synchronizer is disabled.
1 The I/O pin input synchronizer is enabled.