22.8.1 Sleep Configuration

Name: SLEEPCFG
Offset: 0x01
Reset: 0x2
Property: PAC Write-Protection

Bit 76543210 
      SLEEPMODE[2:0] 
Access R/WR/WR/W 
Reset 000 

Bits 2:0 – SLEEPMODE[2:0] Sleep Mode

Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG register due to bridges. Software has to make sure the SLEEPCFG register reads the wanted value before issuing WFI instruction.
ValueNameDefinition
0x0ReservedReserved
0x1ReservedReserved
0x2IDLECPU, AHBx, and APBx clocks are OFF
0x3ReservedReserved
0x4STANDBYALL clocks are OFF, unless requested by sleepwalking peripheral
0x5ReservedReserved
0x6OFFAll power domains are powered OFF
0x7ReservedReserved