CAUTION: This configuration
takes effect immediately. Therefore, users must ensure that no access is performed on
a SRAM sub-block which is switched OFF. When a SRAM sub-block is switched from OFF to
ON state, a delay of 1 µs is required before re-accessing it.
Table 22-7. 64-KB Flash| Value | Name | Definition |
|---|
| 0x0 | 16 KB | 16 KB available |
| 0x1 | 12 KB | 12 KB available |
| 0x2 | 8 KB | 8 KB available |
| 0x3 | 4 KB | 4 KB available |
Table 22-8. 32-KB Flash| Value | Name | Definition |
|---|
| 0x0 | 8 KB | 8 KB available |
| 0x1 | 8 KB | 8 KB available |
| 0x2 | 8 KB | 8 KB available |
| 0x3 | 4 KB | 4 KB available |
Table 22-9. 16-KB Flash (SAM L10)| Value | Name | Definition |
|---|
| 0x0 | 4 KB | 4 KB Available |
| 0x1 | 4 KB | 4 KB Available |
| 0x2 | 4 KB | 4 KB Available |
| 0x3 | 4 KB | 4 KB Available |
Table 22-10. 16-KB Flash (SAM L11)| Value | Name | Definition |
|---|
| 0x0 | 8 KB | 8 KB Available |
| 0x1 | 8 KB | 8 KB Available |
| 0x2 | 8 KB | 8 KB Available |
| 0x3 | 4 KB | 4 KB Available |
