22.8.7 Standby Configuration

Name: STDBYCFG
Offset: 0x08
Reset: 0x0000
Property: PAC Write-Protection

Bit 15141312111098 
    BBIASTR BBIASHS   
Access R/WR/W 
Reset 00 
Bit 76543210 
 VREGSMOD[1:0] DPGPDSW   PDCFG 
Access RRR/WR/W 
Reset 0000 

Bits 7:6 – VREGSMOD[1:0] VREG Switching Mode

Refer to 22.6.4.4 Regulator Automatic Low-Power Mode for details.

ValueNameDescription
0x0 AUTO Automatic Mode
0x1 PERFORMANCE Performance oriented
0x2 LP Low Power consumption oriented

Bit 4 – DPGPDSW Dynamic Power Gating for Switchable Power Domain

ValueDescription
0 Dynamic SleepWalking for switchable power domain is disabled
1 Dynamic SleepWalking for switchable power domain PDSW is enabled

Bit 0 – PDCFG Power Domain Configuration

ValueNameDescription
0x0 DEFAULT In standby mode, all power domain switching are handled by hardware.
0x1 PDSW In standby mode, PDSW is forced ACTIVE.