25.8.6 Voltage Regulator System (VREG) Control
| Name: | VREG |
| Offset: | 0x18 |
| Reset: | 0x00000002 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| VSPER[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| VSVSTEP[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| VREFSEL | LPEFF | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | STDBYPL0 | SEL[1:0] | ENABLE | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 1 | 0 | 0 | 1 | ||||
Bits 31:24 – VSPER[7:0] Voltage Scaling Period
This bitfield sets the period between the voltage steps when the VDDCORE voltage is changing in µs.
If VSPER=0, the period between two voltage steps is 1µs.
Bits 19:16 – VSVSTEP[3:0] Voltage Scaling Voltage Step
This field sets the voltage step height when the VDDCORE voltage is changing to reach the target VDDCORE voltage.
The voltage step is equal to 2VSVSTEP* min_step.
See the Electrical Characteristics chapters for the min_step voltage level.
Bit 9 – VREFSEL Voltage Regulator Voltage Reference Selection
| Value | Description |
|---|---|
| 0 | Selects VREF for the voltage regulator. |
| 1 | Selects ULPVREF for the voltage regulator. |
Bit 8 – LPEFF Low power Mode Efficiency
| Value | Description |
|---|---|
| 0 | The voltage regulator in Low power mode has the default efficiency and supports the whole VDD range (1.62V to 3.63V). |
| 1 | The voltage regulator in Low power mode has the highest efficiency and supports a limited VDD range (2.5V to 3.63V). |
Bit 6 – RUNSTDBY Run in Standby
| Value | Description |
|---|---|
| 0 | The voltage regulator is in low power mode in Standby sleep mode. |
| 1 | The voltage regulator is in normal mode in Standby sleep mode. |
Bit 5 – STDBYPL0 Standby in PL0
| Value | Description |
|---|---|
| 0 | In Standby sleep mode, the voltage regulator remains in the current performance level. |
| 1 | In Standby sleep mode, the voltage regulator is used in PL0. |
Bits 3:2 – SEL[1:0] Voltage Regulator Selection
| Value | Description |
|---|---|
| 0 | The voltage regulator in active mode is a LDO voltage regulator. |
| 1 | The voltage regulator in active mode is a buck converter. |
| 2-3 | Reserved |